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-rw-r--r--src/soc/intel/skylake/romstage/power_state.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 19875346b4..85234b55c9 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -69,6 +69,14 @@ static uint32_t prev_sleep_state(struct chipset_power_state *ps)
}
/* Clear SLP_TYP. */
outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
+ } else {
+ /*
+ * Check for any power failure to determine if this a wake from
+ * S5 because the PCH does not set the WAK_STS bit when waking
+ * from a true G3 state.
+ */
+ if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR))
+ prev_sleep_state = SLEEP_STATE_S5;
}
/*