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-rw-r--r--src/soc/intel/meteorlake/Makefile.inc3
-rw-r--r--src/soc/intel/meteorlake/acpi/gpio.asl178
-rw-r--r--src/soc/intel/meteorlake/gpio.c228
-rw-r--r--src/soc/intel/meteorlake/include/soc/gpio.h18
-rw-r--r--src/soc/intel/meteorlake/include/soc/gpio_defs.h268
-rw-r--r--src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h515
6 files changed, 1210 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/Makefile.inc b/src/soc/intel/meteorlake/Makefile.inc
index 3c0754d42b..147fb59e4c 100644
--- a/src/soc/intel/meteorlake/Makefile.inc
+++ b/src/soc/intel/meteorlake/Makefile.inc
@@ -10,6 +10,7 @@ all-y += i2c.c
all-y += pmutil.c
all-y += spi.c
all-y += uart.c
+all-y += gpio.c
bootblock-y += bootblock/bootblock.c
bootblock-y += bootblock/ioe_die.c
@@ -44,7 +45,9 @@ ramstage-y += systemagent.c
ramstage-y += tcss.c
ramstage-y += xhci.c
ramstage-y += soc_info.c
+
smm-y += elog.c
+smm-y += gpio.c
smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
diff --git a/src/soc/intel/meteorlake/acpi/gpio.asl b/src/soc/intel/meteorlake/acpi/gpio.asl
new file mode 100644
index 0000000000..f7dbc8793d
--- /dev/null
+++ b/src/soc/intel/meteorlake/acpi/gpio.asl
@@ -0,0 +1,178 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/gpio.h>
+#include <soc/gpio_defs.h>
+#include <soc/intel/common/acpi/gpio.asl>
+#include <soc/intel/common/block/acpi/acpi/gpio_op.asl>
+#include <soc/irq.h>
+#include <soc/pcr_ids.h>
+
+Device (GPIO)
+{
+ Name (_HID, CROS_GPIO_NAME)
+ Name (_UID, 0)
+ Name (_DDN, "GPIO Controller")
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, 0, 0, COM0)
+ Memory32Fixed (ReadWrite, 0, 0, COM1)
+ Memory32Fixed (ReadWrite, 0, 0, COM3)
+ Memory32Fixed (ReadWrite, 0, 0, COM4)
+ Memory32Fixed (ReadWrite, 0, 0, COM5)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
+ { GPIO_IRQ14 }
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ /* GPIO Community 0 */
+ CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
+ CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
+ BAS0 = ^^PCRB (PID_GPIOCOM0)
+ LEN0 = GPIO_BASE_SIZE
+
+ /* GPIO Community 1 */
+ CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
+ CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
+ BAS1 = ^^PCRB (PID_GPIOCOM1)
+ LEN1 = GPIO_BASE_SIZE
+
+ /* GPIO Community 3 */
+ CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
+ CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
+ BAS3 = ^^PCRB (PID_GPIOCOM3)
+ LEN3 = GPIO_BASE_SIZE
+
+ /* GPIO Community 4 */
+ CreateDWordField (^RBUF, ^COM4._BAS, BAS4)
+ CreateDWordField (^RBUF, ^COM4._LEN, LEN4)
+ BAS4 = ^^PCRB (PID_GPIOCOM4)
+ LEN4 = GPIO_BASE_SIZE
+
+ /* GPIO Community 5 */
+ CreateDWordField (^RBUF, ^COM5._BAS, BAS5)
+ CreateDWordField (^RBUF, ^COM5._LEN, LEN5)
+ BAS5 = ^^PCRB (PID_GPIOCOM5)
+ LEN5 = GPIO_BASE_SIZE
+
+ Return (RBUF)
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0xF)
+ }
+}
+
+/*
+ * Get GPIO DW0 Address
+ * Arg0 - GPIO Number
+ */
+Method (GADD, 1, NotSerialized)
+{
+ /* GPIO Community 0 */
+ If (Arg0 >= GPIO_COM0_START && Arg0 <= GPIO_COM0_END)
+ {
+ Local0 = PID_GPIOCOM0
+ Local1 = Arg0 - GPIO_COM0_START
+ }
+ /* GPIO Community 1 */
+ If (Arg0 >= GPIO_COM1_START && Arg0 <= GPIO_COM1_END)
+ {
+ Local0 = PID_GPIOCOM1
+ Local1 = Arg0 - GPIO_COM1_START
+ }
+ /* GPIO Community 3 */
+ If (Arg0 >= GPIO_COM3_START && Arg0 <= GPIO_COM3_END)
+ {
+ Local0 = PID_GPIOCOM3
+ Local1 = Arg0 - GPIO_COM3_START
+ }
+ /* GPIO Community 4 */
+ If (Arg0 >= GPIO_COM4_START && Arg0 <= GPIO_COM4_END)
+ {
+ Local0 = PID_GPIOCOM4
+ Local1 = Arg0 - GPIO_COM4_START
+ }
+ /* GPIO Community 5*/
+ If (Arg0 >= GPIO_COM5_START && Arg0 <= GPIO_COM5_END)
+ {
+ Local0 = PID_GPIOCOM5
+ Local1 = Arg0 - GPIO_COM5_START
+ }
+
+ Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
+ Return (Local2)
+}
+
+/*
+ * Return PCR Port ID of GPIO Communities
+ *
+ * Arg0: GPIO Community (0-5)
+ */
+Method (GPID, 1, Serialized)
+{
+ Switch (ToInteger (Arg0))
+ {
+ Case (COMM_0) {
+ Local0 = PID_GPIOCOM0
+ }
+ Case (COMM_1) {
+ Local0 = PID_GPIOCOM1
+ }
+ Case (COMM_3) {
+ Local0 = PID_GPIOCOM3
+ }
+ Case (COMM_4) {
+ Local0 = PID_GPIOCOM4
+ }
+ Case (COMM_5) {
+ Local0 = PID_GPIOCOM5
+ }
+ Default {
+ Return (0)
+ }
+ }
+
+ Return (Local0)
+}
+
+/* GPIO Power Management bits */
+Name(GPMB, Package(TOTAL_GPIO_COMM) {0, 0, 0, 0, 0})
+
+/*
+ * Save GPIO Power Management bits
+ */
+Method (SGPM, 0, Serialized)
+{
+ For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+ {
+ Local1 = GPID (Local0)
+ GPMB[Local0] = PCRR (Local1, GPIO_MISCCFG)
+ }
+}
+
+/*
+ * Restore GPIO Power Management bits
+ */
+Method (RGPM, 0, Serialized)
+{
+ For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+ {
+ CGPM (Local0, DerefOf(GPMB[Local0]))
+ }
+}
+
+/*
+ * Save current setting of GPIO Power Management bits and
+ * enable all Power Management bits for all communities
+ */
+Method (EGPM, 0, Serialized)
+{
+ /* Save current setting and will restore it when resuming */
+ SGPM ()
+ /* Enable PM bits */
+ For (Local0 = 0, Local0 < TOTAL_GPIO_COMM, Local0++)
+ {
+ CGPM (Local0, MISCCFG_GPIO_PM_CONFIG_BITS)
+ }
+}
diff --git a/src/soc/intel/meteorlake/gpio.c b/src/soc/intel/meteorlake/gpio.c
new file mode 100644
index 0000000000..85b04f35e5
--- /dev/null
+++ b/src/soc/intel/meteorlake/gpio.c
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <intelblocks/gpio.h>
+#include <intelblocks/pcr.h>
+#include <soc/pcr_ids.h>
+#include <soc/pmc.h>
+
+#define DEFAULT_VW_BASE 0x10
+
+static const struct reset_mapping rst_map[] = {
+ { .logical = PAD_RESET(RSMRST), .chipset = 0U << 30 },
+ { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
+ { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
+};
+static const struct reset_mapping rst_map_com3[] = {
+ { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
+ { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
+ { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
+ { .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 },
+};
+
+/*
+ * The GPIO pinctrl driver for Meteor Lake on Linux expects 32 GPIOs per pad
+ * group, regardless of whether or not there is a physical pad for each
+ * exposed GPIO number.
+ *
+ * This results in the OS having a sparse GPIO map, and devices that need
+ * to export an ACPI GPIO must use the OS expected number.
+ *
+ * Not all pins are usable as GPIO and those groups do not have a pad base.
+ */
+static const struct pad_group mtl_community0_groups[] = {
+ INTEL_GPP(GPP_PECI, GPP_PECI, GPP_VIDALERT_B), /* GPP_CPU */
+ INTEL_GPP_BASE(GPP_PECI, GPP_V0, GPP_V23, 0), /* GPP_V */
+ INTEL_GPP_BASE(GPP_PECI, GPP_C0, GPP_C23, 32), /* GPP_C */
+};
+
+static const struct vw_entries mtl_community0_vw[] = {
+ {GPP_C0, GPP_C23},
+};
+
+static const struct pad_group mtl_community1_groups[] = {
+ INTEL_GPP_BASE(GPP_A0, GPP_A0, GPP_ESPI_CLK_LPBK, 64), /* GPP_A */
+ INTEL_GPP_BASE(GPP_A0, GPP_E0, GPP_THC0_GSPI_CLK_LPBK, 96), /* GPP_E */
+};
+
+static const struct vw_entries mtl_community1_vw[] = {
+ {GPP_A0, GPP_A20},
+ {GPP_E0, GPP_E23},
+};
+
+static const struct pad_group mtl_community3_groups[] = {
+ INTEL_GPP_BASE(GPP_H0, GPP_H0, GPP_LPI3C0_CLK_LPBK, 128), /* GPP_H */
+ INTEL_GPP_BASE(GPP_H0, GPP_F0, GPP_GSPI0A_CLK_LOOPBK, 160), /* GPP_F */
+ INTEL_GPP(GPP_H0, GPP_SPI0_IO_2, GPP_SPI0_CLK_LOOPBK), /* GPP_SPI0 */
+ INTEL_GPP(GPP_H0, GPP_VGPIO3_USB0, GPP_VGPIO3_THC3), /* GPP_VGPIO3 */
+};
+
+static const struct vw_entries mtl_community3_vw[] = {
+ {GPP_H0, GPP_H23},
+ {GPP_F0, GPP_F23},
+};
+
+static const struct pad_group mtl_community4_groups[] = {
+ INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 192), /* GPP_S */
+ INTEL_GPP(GPP_S0, GPP_JTAG_MBPB0, GPP_JTAG_TRST_B), /* GPP_JTAG */
+};
+
+static const struct pad_group mtl_community5_groups[] = {
+ INTEL_GPP_BASE(GPP_B0, GPP_B0, GPP_ACI3C0_CLK_LPBK, 224), /* GPP_B */
+ INTEL_GPP_BASE(GPP_B0, GPP_D0, GPP_BOOTHALT_B, 256), /* GPP_D */
+ INTEL_GPP(GPP_B0, GPP_VGPIO0, GPP_VGPIO47), /* GPP_VGPIO */
+};
+
+static const struct vw_entries mtl_community5_vw[] = {
+ {GPP_B0, GPP_B23},
+ {GPP_D0, GPP_D23},
+};
+
+static const struct pad_community mtl_communities[] = {
+ [COMM_0] = { /* GPP CPU, V, C */
+ .port = PID_GPIOCOM0,
+ .first_pad = GPIO_COM0_START,
+ .last_pad = GPIO_COM0_END,
+ .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_CPUVC",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = mtl_community0_groups,
+ .num_groups = ARRAY_SIZE(mtl_community0_groups),
+ .vw_base = DEFAULT_VW_BASE,
+ .vw_entries = mtl_community0_vw,
+ .num_vw_entries = ARRAY_SIZE(mtl_community0_vw),
+ },
+ [COMM_1] = { /* GPP A, E */
+ .port = PID_GPIOCOM1,
+ .first_pad = GPIO_COM1_START,
+ .last_pad = GPIO_COM1_END,
+ .num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_AE",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = mtl_community1_groups,
+ .num_groups = ARRAY_SIZE(mtl_community1_groups),
+ .vw_base = DEFAULT_VW_BASE,
+ .vw_entries = mtl_community1_vw,
+ .num_vw_entries = ARRAY_SIZE(mtl_community1_vw),
+ },
+ [COMM_3] = { /* GPP H, F, SPI0, VGPIO3 */
+ .port = PID_GPIOCOM3,
+ .first_pad = GPIO_COM3_START,
+ .last_pad = GPIO_COM3_END,
+ .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_HFSPI0VG3",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map_com3,
+ .num_reset_vals = ARRAY_SIZE(rst_map_com3),
+ .groups = mtl_community3_groups,
+ .num_groups = ARRAY_SIZE(mtl_community3_groups),
+ .vw_base = DEFAULT_VW_BASE,
+ .vw_entries = mtl_community3_vw,
+ .num_vw_entries = ARRAY_SIZE(mtl_community3_vw),
+ },
+ [COMM_4] = { /* GPP S, JTAG */
+ .port = PID_GPIOCOM4,
+ .first_pad = GPIO_COM4_START,
+ .last_pad = GPIO_COM4_END,
+ .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_SJTAG",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = mtl_community4_groups,
+ .num_groups = ARRAY_SIZE(mtl_community4_groups),
+ },
+ [COMM_5] = { /* GPP B, D, VGPIO */
+ .port = PID_GPIOCOM5,
+ .first_pad = GPIO_COM5_START,
+ .last_pad = GPIO_COM5_END,
+ .num_gpi_regs = NUM_GPIO_COM5_GPI_REGS,
+ .pad_cfg_base = PAD_CFG_BASE,
+ .pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET,
+ .host_own_reg_0 = HOSTSW_OWN_REG_0,
+ .gpi_int_sts_reg_0 = GPI_INT_STS_0,
+ .gpi_int_en_reg_0 = GPI_INT_EN_0,
+ .gpi_gpe_sts_reg_0 = GPI_GPE_STS_0,
+ .gpi_gpe_en_reg_0 = GPI_GPE_EN_0,
+ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
+ .gpi_smi_en_reg_0 = GPI_SMI_EN_0,
+ .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0,
+ .gpi_nmi_en_reg_0 = GPI_NMI_EN_0,
+ .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
+ .name = "GPP_BDVG",
+ .acpi_path = "\\_SB.PCI0.GPIO",
+ .reset_map = rst_map,
+ .num_reset_vals = ARRAY_SIZE(rst_map),
+ .groups = mtl_community5_groups,
+ .num_groups = ARRAY_SIZE(mtl_community5_groups),
+ .vw_base = DEFAULT_VW_BASE,
+ .vw_entries = mtl_community5_vw,
+ .num_vw_entries = ARRAY_SIZE(mtl_community5_vw),
+ }
+};
+
+const struct pad_community *soc_gpio_get_community(size_t *num_communities)
+{
+ *num_communities = ARRAY_SIZE(mtl_communities);
+ return mtl_communities;
+}
+
+const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
+{
+ static const struct pmc_to_gpio_route routes[] = {
+ { PMC_GPP_V, GPP_V },
+ { PMC_GPP_C, GPP_C },
+ { PMC_GPP_A, GPP_A },
+ { PMC_GPP_E, GPP_E },
+ { PMC_GPP_H, GPP_H },
+ { PMC_GPP_F, GPP_F },
+ { PMC_GPP_S, GPP_S },
+ { PMC_GPP_B, GPP_B },
+ { PMC_GPP_D, GPP_D },
+ };
+ *num = ARRAY_SIZE(routes);
+ return routes;
+}
diff --git a/src/soc/intel/meteorlake/include/soc/gpio.h b/src/soc/intel/meteorlake/include/soc/gpio.h
new file mode 100644
index 0000000000..50a33a585e
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/gpio.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_GPIO_H_
+#define _SOC_METEORLAKE_GPIO_H_
+
+#include <soc/gpio_defs.h>
+#include <intelblocks/gpio.h>
+
+#define CROS_GPIO_NAME "INTC1083"
+#define CROS_GPIO_DEVICE_NAME "INTC1083:00"
+
+/* Enable GPIO community power management configuration */
+#define MISCCFG_GPIO_PM_CONFIG_BITS (MISCCFG_GPVNNREQEN | \
+ MISCCFG_GPPGCBDPCGEN | MISCCFG_GPSIDEDPCGEN | \
+ MISCCFG_GPRCOMPCDLCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN \
+ | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN)
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/gpio_defs.h b/src/soc/intel/meteorlake/include/soc/gpio_defs.h
new file mode 100644
index 0000000000..3594c56dfe
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/gpio_defs.h
@@ -0,0 +1,268 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_METEORLAKE_GPIO_DEFS_H_
+#define _SOC_METEORLAKE_GPIO_DEFS_H_
+
+#ifndef __ACPI__
+#include <stddef.h>
+#endif
+#include <soc/gpio_soc_defs.h>
+
+#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */
+
+#define NUM_GPIO_COMx_GPI_REGS(n) \
+ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)
+
+#define NUM_GPIO_COM0_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM0_PADS)
+#define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS)
+#define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS)
+#define NUM_GPIO_COM4_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS)
+#define NUM_GPIO_COM5_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS)
+
+#define NUM_GPI_STATUS_REGS \
+ ((NUM_GPIO_COM0_GPI_REGS) +\
+ (NUM_GPIO_COM1_GPI_REGS) +\
+ (NUM_GPIO_COM3_GPI_REGS) +\
+ (NUM_GPIO_COM4_GPI_REGS) +\
+ (NUM_GPIO_COM5_GPI_REGS))
+
+#define PAD_CFG_LOCK_OFFSET 0x110
+
+/*
+ * IOxAPIC IRQs for the GPIOs
+ */
+
+/* Group V */
+#define GPP_V0_IRQ 0x18
+#define GPP_V1_IRQ 0x19
+#define GPP_V2_IRQ 0x1A
+#define GPP_V3_IRQ 0x1B
+#define GPP_V4_IRQ 0x1C
+#define GPP_V5_IRQ 0x1D
+#define GPP_V6_IRQ 0x1E
+#define GPP_V7_IRQ 0x1F
+#define GPP_V8_IRQ 0x20
+#define GPP_V9_IRQ 0x21
+#define GPP_V10_IRQ 0x22
+#define GPP_V11_IRQ 0x23
+#define GPP_V12_IRQ 0x24
+#define GPP_V13_IRQ 0x25
+#define GPP_V14_IRQ 0x26
+#define GPP_V15_IRQ 0x27
+#define GPP_V16_IRQ 0x28
+#define GPP_V17_IRQ 0x29
+#define GPP_V18_IRQ 0x2A
+#define GPP_V19_IRQ 0x2B
+#define GPP_V20_IRQ 0x2C
+#define GPP_V21_IRQ 0x2D
+#define GPP_V22_IRQ 0x2E
+#define GPP_V23_IRQ 0x2F
+
+/* Group C */
+#define GPP_C0_IRQ 0x30
+#define GPP_C1_IRQ 0x31
+#define GPP_C2_IRQ 0x32
+#define GPP_C3_IRQ 0x33
+#define GPP_C4_IRQ 0x34
+#define GPP_C5_IRQ 0x35
+#define GPP_C6_IRQ 0x36
+#define GPP_C7_IRQ 0x37
+#define GPP_C8_IRQ 0x38
+#define GPP_C9_IRQ 0x39
+#define GPP_C10_IRQ 0x3A
+#define GPP_C11_IRQ 0x3B
+#define GPP_C12_IRQ 0x3C
+#define GPP_C13_IRQ 0x3D
+#define GPP_C14_IRQ 0x3E
+#define GPP_C15_IRQ 0x3F
+#define GPP_C16_IRQ 0x40
+#define GPP_C17_IRQ 0x41
+#define GPP_C18_IRQ 0x42
+#define GPP_C19_IRQ 0x43
+#define GPP_C20_IRQ 0x44
+#define GPP_C21_IRQ 0x45
+#define GPP_C22_IRQ 0x46
+#define GPP_C23_IRQ 0x47
+
+/* Group A */
+#define GPP_A0_IRQ 0x48
+#define GPP_A1_IRQ 0x49
+#define GPP_A2_IRQ 0x4A
+#define GPP_A3_IRQ 0x4B
+#define GPP_A4_IRQ 0x4C
+#define GPP_A5_IRQ 0x4D
+#define GPP_A6_IRQ 0x4E
+#define GPP_A7_IRQ 0x4F
+#define GPP_A8_IRQ 0x50
+#define GPP_A9_IRQ 0x51
+#define GPP_A10_IRQ 0x52
+#define GPP_A11_IRQ 0x53
+#define GPP_A12_IRQ 0x54
+#define GPP_A13_IRQ 0x55
+#define GPP_A14_IRQ 0x56
+#define GPP_A15_IRQ 0x57
+#define GPP_A16_IRQ 0x58
+#define GPP_A17_IRQ 0x59
+#define GPP_A18_IRQ 0x5A
+#define GPP_A19_IRQ 0x5B
+#define GPP_A20_IRQ 0x5C
+#define GPP_A21_IRQ 0x5D
+#define GPP_A22_IRQ 0x5E
+#define GPP_A23_IRQ 0x5F
+
+/* Group E */
+#define GPP_E0_IRQ 0x60
+#define GPP_E1_IRQ 0x61
+#define GPP_E2_IRQ 0x62
+#define GPP_E3_IRQ 0x63
+#define GPP_E4_IRQ 0x64
+#define GPP_E5_IRQ 0x65
+#define GPP_E6_IRQ 0x66
+#define GPP_E7_IRQ 0x67
+#define GPP_E8_IRQ 0x68
+#define GPP_E9_IRQ 0x69
+#define GPP_E10_IRQ 0x6A
+#define GPP_E11_IRQ 0x6B
+#define GPP_E12_IRQ 0x6C
+#define GPP_E13_IRQ 0x6D
+#define GPP_E14_IRQ 0x6E
+#define GPP_E15_IRQ 0x6F
+#define GPP_E16_IRQ 0x70
+#define GPP_E17_IRQ 0x71
+#define GPP_E18_IRQ 0x72
+#define GPP_E19_IRQ 0x73
+#define GPP_E20_IRQ 0x74
+#define GPP_E21_IRQ 0x75
+#define GPP_E22_IRQ 0x76
+#define GPP_E23_IRQ 0x77
+
+/* Group H */
+#define GPP_H0_IRQ 0x18
+#define GPP_H1_IRQ 0x19
+#define GPP_H2_IRQ 0x1A
+#define GPP_H3_IRQ 0x1B
+#define GPP_H4_IRQ 0x1C
+#define GPP_H5_IRQ 0x1D
+#define GPP_H6_IRQ 0x1E
+#define GPP_H7_IRQ 0x1F
+#define GPP_H8_IRQ 0x20
+#define GPP_H9_IRQ 0x21
+#define GPP_H10_IRQ 0x22
+#define GPP_H11_IRQ 0x23
+#define GPP_H12_IRQ 0x24
+#define GPP_H13_IRQ 0x25
+#define GPP_H14_IRQ 0x26
+#define GPP_H15_IRQ 0x27
+#define GPP_H16_IRQ 0x28
+#define GPP_H17_IRQ 0x29
+#define GPP_H18_IRQ 0x2A
+#define GPP_H19_IRQ 0x2B
+#define GPP_H20_IRQ 0x2C
+#define GPP_H21_IRQ 0x2D
+#define GPP_H22_IRQ 0x2E
+#define GPP_H23_IRQ 0x2F
+
+/* Group F */
+#define GPP_F0_IRQ 0x30
+#define GPP_F1_IRQ 0x31
+#define GPP_F2_IRQ 0x32
+#define GPP_F3_IRQ 0x33
+#define GPP_F4_IRQ 0x34
+#define GPP_F5_IRQ 0x35
+#define GPP_F6_IRQ 0x36
+#define GPP_F7_IRQ 0x37
+#define GPP_F8_IRQ 0x38
+#define GPP_F9_IRQ 0x39
+#define GPP_F10_IRQ 0x3A
+#define GPP_F11_IRQ 0x3B
+#define GPP_F12_IRQ 0x3C
+#define GPP_F13_IRQ 0x3D
+#define GPP_F14_IRQ 0x3E
+#define GPP_F15_IRQ 0x3F
+#define GPP_F16_IRQ 0x40
+#define GPP_F17_IRQ 0x41
+#define GPP_F18_IRQ 0x42
+#define GPP_F19_IRQ 0x43
+#define GPP_F20_IRQ 0x44
+#define GPP_F21_IRQ 0x45
+#define GPP_F22_IRQ 0x46
+#define GPP_F23_IRQ 0x47
+
+/* Group S */
+#define GPP_S0_IRQ 0x50
+#define GPP_S1_IRQ 0x51
+#define GPP_S2_IRQ 0x52
+#define GPP_S3_IRQ 0x53
+#define GPP_S4_IRQ 0x54
+#define GPP_S5_IRQ 0x55
+#define GPP_S6_IRQ 0x56
+#define GPP_S7_IRQ 0x57
+
+/* Group B */
+#define GPP_B0_IRQ 0x58
+#define GPP_B1_IRQ 0x59
+#define GPP_B2_IRQ 0x5A
+#define GPP_B3_IRQ 0x5B
+#define GPP_B4_IRQ 0x5C
+#define GPP_B5_IRQ 0x5D
+#define GPP_B6_IRQ 0x5E
+#define GPP_B7_IRQ 0x5F
+#define GPP_B8_IRQ 0x60
+#define GPP_B9_IRQ 0x61
+#define GPP_B10_IRQ 0x62
+#define GPP_B11_IRQ 0x63
+#define GPP_B12_IRQ 0x64
+#define GPP_B13_IRQ 0x65
+#define GPP_B14_IRQ 0x66
+#define GPP_B15_IRQ 0x67
+#define GPP_B16_IRQ 0x68
+#define GPP_B17_IRQ 0x69
+#define GPP_B18_IRQ 0x6A
+#define GPP_B19_IRQ 0x6B
+#define GPP_B20_IRQ 0x6C
+#define GPP_B21_IRQ 0x6D
+#define GPP_B22_IRQ 0x6E
+#define GPP_B23_IRQ 0x6F
+
+/* Group D */
+#define GPP_D0_IRQ 0x70
+#define GPP_D1_IRQ 0x71
+#define GPP_D2_IRQ 0x72
+#define GPP_D3_IRQ 0x73
+#define GPP_D4_IRQ 0x74
+#define GPP_D5_IRQ 0x75
+#define GPP_D6_IRQ 0x76
+#define GPP_D7_IRQ 0x77
+#define GPP_D8_IRQ 0x18
+#define GPP_D9_IRQ 0x19
+#define GPP_D10_IRQ 0x1A
+#define GPP_D11_IRQ 0x1B
+#define GPP_D12_IRQ 0x1C
+#define GPP_D13_IRQ 0x1D
+#define GPP_D14_IRQ 0x1E
+#define GPP_D15_IRQ 0x1F
+#define GPP_D16_IRQ 0x20
+#define GPP_D17_IRQ 0x21
+#define GPP_D18_IRQ 0x22
+#define GPP_D19_IRQ 0x23
+#define GPP_D20_IRQ 0x24
+#define GPP_D21_IRQ 0x25
+#define GPP_D22_IRQ 0x26
+#define GPP_D23_IRQ 0x27
+
+/* Register defines. */
+#define GPIO_MISCCFG 0x10
+#define GPE_DW_SHIFT 8
+#define GPE_DW_MASK 0xfff00
+#define HOSTSW_OWN_REG_0 0x140
+#define GPI_INT_STS_0 0x200
+#define GPI_INT_EN_0 0x210
+#define GPI_GPE_STS_0 0x230
+#define GPI_GPE_EN_0 0x250
+#define GPI_SMI_STS_0 0x270
+#define GPI_SMI_EN_0 0x290
+#define GPI_NMI_STS_0 0x2b0
+#define GPI_NMI_EN_0 0x2d0
+#define PAD_CFG_BASE 0x600
+
+#endif
diff --git a/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h b/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h
new file mode 100644
index 0000000000..9f7cd9643c
--- /dev/null
+++ b/src/soc/intel/meteorlake/include/soc/gpio_soc_defs.h
@@ -0,0 +1,515 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _SOC_METEORLAKE_GPIO_SOC_DEFS_H_
+#define _SOC_METEORLAKE_GPIO_SOC_DEFS_H_
+
+#define INC(x) ((x) + 1)
+
+/*
+ * Most of the fixed numbers and macros are based on the GPP groups.
+ * The GPIO groups are accessed through register blocks called
+ * communities.
+ */
+#define GPP_V 0x0
+#define GPP_C INC(GPP_V)
+#define GPP_A INC(GPP_C)
+#define GPP_E INC(GPP_A)
+#define GPP_H INC(GPP_E)
+#define GPP_F INC(GPP_H)
+#define GPP_VGPIO3 INC(GPP_F)
+#define GPP_VGPIO INC(GPP_VGPIO3)
+#define GPP_S INC(GPP_VGPIO)
+#define GPP_B INC(GPP_S)
+#define GPP_D INC(GPP_B)
+
+#define GPIO_MAX_NUM_PER_GROUP 26
+
+#define COMM_0 0
+#define COMM_1 INC(COMM_0)
+#define COMM_3 INC(COMM_1)
+#define COMM_4 INC(COMM_3)
+#define COMM_5 INC(COMM_4)
+
+/*
+ * GPIOs are ordered monotonically increasing to match ACPI/OS driver.
+ */
+/*
+ * +----------------------------+
+ * | Group CPU |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 0 |
+ * +------------------+---------+
+ * | Pad End Number | 4 |
+ * +------------------+---------+
+ */
+#define GPP_PECI 0
+#define GPP_UFS_RST_B INC(GPP_PECI)
+#define GPP_VIDSOUT INC(GPP_UFS_RST_B)
+#define GPP_VIDSCK INC(GPP_VIDSOUT)
+#define GPP_VIDALERT_B INC(GPP_VIDSCK)
+
+/*
+ * +----------------------------+
+ * | Group V |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 5 |
+ * +------------------+---------+
+ * | Pad End Number | 28 |
+ * +------------------+---------+
+ */
+#define GPP_V0 INC(GPP_VIDALERT_B)
+#define GPP_V1 INC(GPP_V0)
+#define GPP_V2 INC(GPP_V1)
+#define GPP_V3 INC(GPP_V2)
+#define GPP_V4 INC(GPP_V3)
+#define GPP_V5 INC(GPP_V4)
+#define GPP_V6 INC(GPP_V5)
+#define GPP_V7 INC(GPP_V6)
+#define GPP_V8 INC(GPP_V7)
+#define GPP_V9 INC(GPP_V8)
+#define GPP_V10 INC(GPP_V9)
+#define GPP_V11 INC(GPP_V10)
+#define GPP_V12 INC(GPP_V11)
+#define GPP_V13 INC(GPP_V12)
+#define GPP_V14 INC(GPP_V13)
+#define GPP_V15 INC(GPP_V14)
+#define GPP_V16 INC(GPP_V15)
+#define GPP_V17 INC(GPP_V16)
+#define GPP_V18 INC(GPP_V17)
+#define GPP_V19 INC(GPP_V18)
+#define GPP_V20 INC(GPP_V19)
+#define GPP_V21 INC(GPP_V20)
+#define GPP_V22 INC(GPP_V21)
+#define GPP_V23 INC(GPP_V22)
+
+/*
+ * +----------------------------+
+ * | Group C |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 29 |
+ * +------------------+---------+
+ * | Pad End Number | 52 |
+ * +------------------+---------+
+ */
+#define GPP_C0 INC(GPP_V23)
+#define GPP_C1 INC(GPP_C0)
+#define GPP_C2 INC(GPP_C1)
+#define GPP_C3 INC(GPP_C2)
+#define GPP_C4 INC(GPP_C3)
+#define GPP_C5 INC(GPP_C4)
+#define GPP_C6 INC(GPP_C5)
+#define GPP_C7 INC(GPP_C6)
+#define GPP_C8 INC(GPP_C7)
+#define GPP_C9 INC(GPP_C8)
+#define GPP_C10 INC(GPP_C9)
+#define GPP_C11 INC(GPP_C10)
+#define GPP_C12 INC(GPP_C11)
+#define GPP_C13 INC(GPP_C12)
+#define GPP_C14 INC(GPP_C13)
+#define GPP_C15 INC(GPP_C14)
+#define GPP_C16 INC(GPP_C15)
+#define GPP_C17 INC(GPP_C16)
+#define GPP_C18 INC(GPP_C17)
+#define GPP_C19 INC(GPP_C18)
+#define GPP_C20 INC(GPP_C19)
+#define GPP_C21 INC(GPP_C20)
+#define GPP_C22 INC(GPP_C21)
+#define GPP_C23 INC(GPP_C22)
+
+#define GPIO_COM0_START GPP_PECI
+#define GPIO_COM0_END GPP_C23
+#define NUM_GPIO_COM0_PADS (GPP_C23 - GPP_PECI + 1)
+
+/*
+ * +----------------------------+
+ * | Group A |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 53 |
+ * +------------------+---------+
+ * | Pad End Number | 77 |
+ * +------------------+---------+
+ */
+#define GPP_A0 INC(GPP_C23)
+#define GPP_A1 INC(GPP_A0)
+#define GPP_A2 INC(GPP_A1)
+#define GPP_A3 INC(GPP_A2)
+#define GPP_A4 INC(GPP_A3)
+#define GPP_A5 INC(GPP_A4)
+#define GPP_A6 INC(GPP_A5)
+#define GPP_A7 INC(GPP_A6)
+#define GPP_A8 INC(GPP_A7)
+#define GPP_A9 INC(GPP_A8)
+#define GPP_A10 INC(GPP_A9)
+#define GPP_A11 INC(GPP_A10)
+#define GPP_A12 INC(GPP_A11)
+#define GPP_A13 INC(GPP_A12)
+#define GPP_A14 INC(GPP_A13)
+#define GPP_A15 INC(GPP_A14)
+#define GPP_A16 INC(GPP_A15)
+#define GPP_A17 INC(GPP_A16)
+#define GPP_A18 INC(GPP_A17)
+#define GPP_A19 INC(GPP_A18)
+#define GPP_A20 INC(GPP_A19)
+#define GPP_A21 INC(GPP_A20)
+#define GPP_A22 INC(GPP_A21)
+#define GPP_A23 INC(GPP_A22)
+#define GPP_ESPI_CLK_LPBK INC(GPP_A23)
+
+/*
+ * +----------------------------+
+ * | Group E |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 78 |
+ * +------------------+---------+
+ * | Pad End Number | 102 |
+ * +------------------+---------+
+ */
+#define GPP_E0 INC(GPP_ESPI_CLK_LPBK)
+#define GPP_E1 INC(GPP_E0)
+#define GPP_E2 INC(GPP_E1)
+#define GPP_E3 INC(GPP_E2)
+#define GPP_E4 INC(GPP_E3)
+#define GPP_E5 INC(GPP_E4)
+#define GPP_E6 INC(GPP_E5)
+#define GPP_E7 INC(GPP_E6)
+#define GPP_E8 INC(GPP_E7)
+#define GPP_E9 INC(GPP_E8)
+#define GPP_E10 INC(GPP_E9)
+#define GPP_E11 INC(GPP_E10)
+#define GPP_E12 INC(GPP_E11)
+#define GPP_E13 INC(GPP_E12)
+#define GPP_E14 INC(GPP_E13)
+#define GPP_E15 INC(GPP_E14)
+#define GPP_E16 INC(GPP_E15)
+#define GPP_E17 INC(GPP_E16)
+#define GPP_E18 INC(GPP_E17)
+#define GPP_E19 INC(GPP_E18)
+#define GPP_E20 INC(GPP_E19)
+#define GPP_E21 INC(GPP_E20)
+#define GPP_E22 INC(GPP_E21)
+#define GPP_E23 INC(GPP_E22)
+#define GPP_THC0_GSPI_CLK_LPBK INC(GPP_E23)
+
+#define GPIO_COM1_START GPP_A0
+#define GPIO_COM1_END GPP_THC0_GSPI_CLK_LPBK
+#define NUM_GPIO_COM1_PADS (GPP_THC0_GSPI_CLK_LPBK - GPP_A0 + 1)
+
+/*
+ * +----------------------------+
+ * | Group H |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 103 |
+ * +------------------+---------+
+ * | Pad End Number | 128 |
+ * +------------------+---------+
+ */
+#define GPP_H0 INC(GPP_THC0_GSPI_CLK_LPBK)
+#define GPP_H1 INC(GPP_H0)
+#define GPP_H2 INC(GPP_H1)
+#define GPP_H3 INC(GPP_H2)
+#define GPP_H4 INC(GPP_H3)
+#define GPP_H5 INC(GPP_H4)
+#define GPP_H6 INC(GPP_H5)
+#define GPP_H7 INC(GPP_H6)
+#define GPP_H8 INC(GPP_H7)
+#define GPP_H9 INC(GPP_H8)
+#define GPP_H10 INC(GPP_H9)
+#define GPP_H11 INC(GPP_H10)
+#define GPP_H12 INC(GPP_H11)
+#define GPP_H13 INC(GPP_H12)
+#define GPP_H14 INC(GPP_H13)
+#define GPP_H15 INC(GPP_H14)
+#define GPP_H16 INC(GPP_H15)
+#define GPP_H17 INC(GPP_H16)
+#define GPP_H18 INC(GPP_H17)
+#define GPP_H19 INC(GPP_H18)
+#define GPP_H20 INC(GPP_H19)
+#define GPP_H21 INC(GPP_H20)
+#define GPP_H22 INC(GPP_H21)
+#define GPP_H23 INC(GPP_H22)
+#define GPP_LPI3C1_CLK_LPBK INC(GPP_H23)
+#define GPP_LPI3C0_CLK_LPBK INC(GPP_LPI3C1_CLK_LPBK)
+
+/*
+ * +----------------------------+
+ * | Group F |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 129 |
+ * +------------------+---------+
+ * | Pad End Number | 154 |
+ * +------------------+---------+
+ */
+#define GPP_F0 INC(GPP_LPI3C0_CLK_LPBK)
+#define GPP_F1 INC(GPP_F0)
+#define GPP_F2 INC(GPP_F1)
+#define GPP_F3 INC(GPP_F2)
+#define GPP_F4 INC(GPP_F3)
+#define GPP_F5 INC(GPP_F4)
+#define GPP_F6 INC(GPP_F5)
+#define GPP_F7 INC(GPP_F6)
+#define GPP_F8 INC(GPP_F7)
+#define GPP_F9 INC(GPP_F8)
+#define GPP_F10 INC(GPP_F9)
+#define GPP_F11 INC(GPP_F10)
+#define GPP_F12 INC(GPP_F11)
+#define GPP_F13 INC(GPP_F12)
+#define GPP_F14 INC(GPP_F13)
+#define GPP_F15 INC(GPP_F14)
+#define GPP_F16 INC(GPP_F15)
+#define GPP_F17 INC(GPP_F16)
+#define GPP_F18 INC(GPP_F17)
+#define GPP_F19 INC(GPP_F18)
+#define GPP_F20 INC(GPP_F19)
+#define GPP_F21 INC(GPP_F20)
+#define GPP_F22 INC(GPP_F21)
+#define GPP_F23 INC(GPP_F22)
+#define GPP_THC1_GSPI1_CLK_LPBK INC(GPP_F23)
+#define GPP_GSPI0A_CLK_LOOPBK INC(GPP_THC1_GSPI1_CLK_LPBK)
+
+/*
+ * +----------------------------+
+ * | Group SPI0 |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 155 |
+ * +------------------+---------+
+ * | Pad End Number | 169 |
+ * +------------------+---------+
+ */
+#define GPP_SPI0_IO_2 INC(GPP_GSPI0A_CLK_LOOPBK)
+#define GPP_SPI0_IO_3 INC(GPP_SPI0_IO_2)
+#define GPP_SPI0_MOSI_IO_0 INC(GPP_SPI0_IO_3)
+#define GPP_SPI0_MOSI_IO_1 INC(GPP_SPI0_MOSI_IO_0)
+#define GPP_SPI0_TPM_CS_B INC(GPP_SPI0_MOSI_IO_1)
+#define GPP_SPI0_FLASH_0_CS_B INC(GPP_SPI0_TPM_CS_B)
+#define GPP_SPI0_FLASH_1_CS_B INC(GPP_SPI0_FLASH_0_CS_B)
+#define GPP_SPI0_CLK INC(GPP_SPI0_FLASH_1_CS_B)
+#define GPP_BKLTEN INC(GPP_SPI0_CLK)
+#define GPP_BKLTCTL INC(GPP_BKLTEN)
+#define GPP_VDDEN INC(GPP_BKLTCTL)
+#define GPP_SYS_PWROK INC(GPP_VDDEN)
+#define GPP_SYS_RESET_B INC(GPP_SYS_PWROK)
+#define GPP_MLK_RST_B INC(GPP_SYS_RESET_B)
+#define GPP_SPI0_CLK_LOOPBK INC(GPP_MLK_RST_B)
+
+/*
+ * +----------------------------+
+ * | Group VGPIO3 |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 170 |
+ * +------------------+---------+
+ * | Pad End Number | 183 |
+ * +------------------+---------+
+ */
+#define GPP_VGPIO3_USB0 INC(GPP_SPI0_CLK_LOOPBK)
+#define GPP_VGPIO3_USB1 INC(GPP_VGPIO3_USB0)
+#define GPP_VGPIO3_USB2 INC(GPP_VGPIO3_USB1)
+#define GPP_VGPIO3_USB3 INC(GPP_VGPIO3_USB2)
+#define GPP_VGPIO3_USB4 INC(GPP_VGPIO3_USB3)
+#define GPP_VGPIO3_USB5 INC(GPP_VGPIO3_USB4)
+#define GPP_VGPIO3_USB6 INC(GPP_VGPIO3_USB5)
+#define GPP_VGPIO3_USB7 INC(GPP_VGPIO3_USB6)
+#define GPP_VGPIO3_TS0 INC(GPP_VGPIO3_USB7)
+#define GPP_VGPIO3_TS1 INC(GPP_VGPIO3_TS0)
+#define GPP_VGPIO3_THC0 INC(GPP_VGPIO3_TS1)
+#define GPP_VGPIO3_THC1 INC(GPP_VGPIO3_THC0)
+#define GPP_VGPIO3_THC2 INC(GPP_VGPIO3_THC1)
+#define GPP_VGPIO3_THC3 INC(GPP_VGPIO3_THC2)
+
+#define GPIO_COM3_START GPP_H0
+#define GPIO_COM3_END GPP_VGPIO3_THC3
+#define NUM_GPIO_COM3_PADS (GPP_VGPIO3_THC3 - GPP_H0 + 1)
+
+/*
+ * +----------------------------+
+ * | Group S |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 184 |
+ * +------------------+---------+
+ * | Pad End Number | 191 |
+ * +------------------+---------+
+ */
+#define GPP_S0 INC(GPP_VGPIO3_THC3)
+#define GPP_S1 INC(GPP_S0)
+#define GPP_S2 INC(GPP_S1)
+#define GPP_S3 INC(GPP_S2)
+#define GPP_S4 INC(GPP_S3)
+#define GPP_S5 INC(GPP_S4)
+#define GPP_S6 INC(GPP_S5)
+#define GPP_S7 INC(GPP_S6)
+
+/*
+ * +----------------------------+
+ * | Group JTAG |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 192 |
+ * +------------------+---------+
+ * | Pad End Number | 203 |
+ * +------------------+---------+
+ */
+#define GPP_JTAG_MBPB0 INC(GPP_S7)
+#define GPP_JTAG_MBPB1 INC(GPP_JTAG_MBPB0)
+#define GPP_JTAG_MBPB2 INC(GPP_JTAG_MBPB1)
+#define GPP_JTAG_MBPB3 INC(GPP_JTAG_MBPB2)
+#define GPP_JTAG_TD0 INC(GPP_JTAG_MBPB3)
+#define GPP_PRDY_B INC(GPP_JTAG_TD0)
+#define GPP_PREQ_B INC(GPP_PRDY_B)
+#define GPP_JTAG_TDI INC(GPP_PREQ_B)
+#define GPP_JTAG_TMS INC(GPP_JTAG_TDI)
+#define GPP_JTAG_TCK INC(GPP_JTAG_TMS)
+#define GPP_DBG_PMODE INC(GPP_JTAG_TCK)
+#define GPP_JTAG_TRST_B INC(GPP_DBG_PMODE)
+
+#define GPIO_COM4_START GPP_S0
+#define GPIO_COM4_END GPP_JTAG_TRST_B
+#define NUM_GPIO_COM4_PADS (GPP_JTAG_TRST_B - GPP_S0 + 1)
+
+/*
+ * +----------------------------+
+ * | Group B |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 204 |
+ * +------------------+---------+
+ * | Pad End Number | 228 |
+ * +------------------+---------+
+ */
+#define GPP_B0 INC(GPP_JTAG_TRST_B)
+#define GPP_B1 INC(GPP_B0)
+#define GPP_B2 INC(GPP_B1)
+#define GPP_B3 INC(GPP_B2)
+#define GPP_B4 INC(GPP_B3)
+#define GPP_B5 INC(GPP_B4)
+#define GPP_B6 INC(GPP_B5)
+#define GPP_B7 INC(GPP_B6)
+#define GPP_B8 INC(GPP_B7)
+#define GPP_B9 INC(GPP_B8)
+#define GPP_B10 INC(GPP_B9)
+#define GPP_B11 INC(GPP_B10)
+#define GPP_B12 INC(GPP_B11)
+#define GPP_B13 INC(GPP_B12)
+#define GPP_B14 INC(GPP_B13)
+#define GPP_B15 INC(GPP_B14)
+#define GPP_B16 INC(GPP_B15)
+#define GPP_B17 INC(GPP_B16)
+#define GPP_B18 INC(GPP_B17)
+#define GPP_B19 INC(GPP_B18)
+#define GPP_B20 INC(GPP_B19)
+#define GPP_B21 INC(GPP_B20)
+#define GPP_B22 INC(GPP_B21)
+#define GPP_B23 INC(GPP_B22)
+#define GPP_ACI3C0_CLK_LPBK INC(GPP_B23)
+
+/*
+ * +----------------------------+
+ * | Group D |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 229 |
+ * +------------------+---------+
+ * | Pad End Number | 253 |
+ * +------------------+---------+
+ */
+#define GPP_D0 INC(GPP_ACI3C0_CLK_LPBK)
+#define GPP_D1 INC(GPP_D0)
+#define GPP_D2 INC(GPP_D1)
+#define GPP_D3 INC(GPP_D2)
+#define GPP_D4 INC(GPP_D3)
+#define GPP_D5 INC(GPP_D4)
+#define GPP_D6 INC(GPP_D5)
+#define GPP_D7 INC(GPP_D6)
+#define GPP_D8 INC(GPP_D7)
+#define GPP_D9 INC(GPP_D8)
+#define GPP_D10 INC(GPP_D9)
+#define GPP_D11 INC(GPP_D10)
+#define GPP_D12 INC(GPP_D11)
+#define GPP_D13 INC(GPP_D12)
+#define GPP_D14 INC(GPP_D13)
+#define GPP_D15 INC(GPP_D14)
+#define GPP_D16 INC(GPP_D15)
+#define GPP_D17 INC(GPP_D16)
+#define GPP_D18 INC(GPP_D17)
+#define GPP_D19 INC(GPP_D18)
+#define GPP_D20 INC(GPP_D19)
+#define GPP_D21 INC(GPP_D20)
+#define GPP_D22 INC(GPP_D21)
+#define GPP_D23 INC(GPP_D22)
+#define GPP_BOOTHALT_B INC(GPP_D23)
+
+/*
+ * +----------------------------+
+ * | Group VGPIO |
+ * +------------------+---------+
+ * | | MTL-M/P |
+ * +------------------+---------+
+ * | Pad Start Number | 254 |
+ * +------------------+---------+
+ * | Pad End Number | 288 |
+ * +------------------+---------+
+ */
+#define GPP_VGPIO0 INC(GPP_BOOTHALT_B)
+#define GPP_VGPIO4 INC(GPP_VGPIO0)
+#define GPP_VGPIO5 INC(GPP_VGPIO4)
+#define GPP_VGPIO6 INC(GPP_VGPIO5)
+#define GPP_VGPIO7 INC(GPP_VGPIO6)
+#define GPP_VGPIO8 INC(GPP_VGPIO7)
+#define GPP_VGPIO9 INC(GPP_VGPIO8)
+#define GPP_VGPIO10 INC(GPP_VGPIO9)
+#define GPP_VGPIO11 INC(GPP_VGPIO10)
+#define GPP_VGPIO12 INC(GPP_VGPIO11)
+#define GPP_VGPIO13 INC(GPP_VGPIO12)
+#define GPP_VGPIO18 INC(GPP_VGPIO13)
+#define GPP_VGPIO19 INC(GPP_VGPIO18)
+#define GPP_VGPIO20 INC(GPP_VGPIO19)
+#define GPP_VGPIO21 INC(GPP_VGPIO20)
+#define GPP_VGPIO22 INC(GPP_VGPIO21)
+#define GPP_VGPIO23 INC(GPP_VGPIO22)
+#define GPP_VGPIO24 INC(GPP_VGPIO23)
+#define GPP_VGPIO25 INC(GPP_VGPIO24)
+#define GPP_VGPIO30 INC(GPP_VGPIO25)
+#define GPP_VGPIO31 INC(GPP_VGPIO30)
+#define GPP_VGPIO32 INC(GPP_VGPIO31)
+#define GPP_VGPIO33 INC(GPP_VGPIO32)
+#define GPP_VGPIO34 INC(GPP_VGPIO33)
+#define GPP_VGPIO35 INC(GPP_VGPIO34)
+#define GPP_VGPIO36 INC(GPP_VGPIO35)
+#define GPP_VGPIO37 INC(GPP_VGPIO36)
+#define GPP_VGPIO40 INC(GPP_VGPIO37)
+#define GPP_VGPIO41 INC(GPP_VGPIO40)
+#define GPP_VGPIO42 INC(GPP_VGPIO41)
+#define GPP_VGPIO43 INC(GPP_VGPIO42)
+#define GPP_VGPIO44 INC(GPP_VGPIO43)
+#define GPP_VGPIO45 INC(GPP_VGPIO44)
+#define GPP_VGPIO46 INC(GPP_VGPIO45)
+#define GPP_VGPIO47 INC(GPP_VGPIO46)
+
+#define GPIO_COM5_START GPP_B0
+#define GPIO_COM5_END GPP_VGPIO47
+#define NUM_GPIO_COM5_PADS (GPP_VGPIO47 - GPP_B0 + 1)
+
+#define TOTAL_GPIO_COMM (COMM_5 + 1)
+#define TOTAL_PADS (GPIO_COM5_END + 1)
+
+#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 15:53:46 +0000