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-rw-r--r--src/soc/intel/skylake/romstage/uart.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
index c53643abc6..afc8c63004 100644
--- a/src/soc/intel/skylake/romstage/uart.c
+++ b/src/soc/intel/skylake/romstage/uart.c
@@ -57,8 +57,9 @@ void pch_uart_init(void)
write32(base + SIO_REG_PPR_CLOCK, tmp);
/* Put UART2 in byte access mode for 16550 compatibility */
- pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0,
- SIO_PCH_LEGACY_UART2);
+ if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL8250MEM_32))
+ pcr_andthenor32(PID_SERIALIO,
+ R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, SIO_PCH_LEGACY_UART2);
/* Configure GPIO for UART2 in native mode*/
uartgpioinit(FALSE);