diff options
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/cannonlake/uart.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index cb1273d399..af224eb9ce 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -27,6 +27,10 @@ #include <soc/pcr_ids.h> #include <soc/iomap.h> +/* Serial IO UART controller legacy mode */ +#define PCR_SERIAL_IO_GPPRVRW7 0x618 +#define PCR_SIO_PCH_LEGACY_UART(idx) (1 << (idx)) + static const struct port { struct pad_config pads[2]; /* just TX and RX */ device_t dev; @@ -55,6 +59,19 @@ void pch_uart_init(void) base = uart_platform_base(CONFIG_UART_FOR_CONSOLE); uart_common_init(p->dev, base); + + /* Put UART2 in byte access mode for 16550 compatibility */ + if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) { + pcr_write32(PID_SERIALIO, PCR_SERIAL_IO_GPPRVRW7, + PCR_SIO_PCH_LEGACY_UART(CONFIG_UART_FOR_CONSOLE)); + + /* + * Dummy read after setting any of GPPRVRW7. + * Required for UART 16550 8-bit Legacy mode to become active + */ + lpss_clk_read(base); + } + gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); } |