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-rw-r--r--src/soc/intel/broadwell/include/soc/iomap.h7
-rw-r--r--src/soc/intel/broadwell/pei_data.c8
2 files changed, 4 insertions, 11 deletions
diff --git a/src/soc/intel/broadwell/include/soc/iomap.h b/src/soc/intel/broadwell/include/soc/iomap.h
index 3a2cafef8a..0f9f38f145 100644
--- a/src/soc/intel/broadwell/include/soc/iomap.h
+++ b/src/soc/intel/broadwell/include/soc/iomap.h
@@ -13,11 +13,4 @@
#define GPIO_BASE_ADDRESS 0x1400
#define GPIO_BASE_SIZE 0x400
-/* Temporary addresses used in romstage */
-#define EARLY_GTT_BAR 0xe0000000
-#define EARLY_XHCI_BAR 0xd7000000
-#define EARLY_EHCI_BAR CONFIG_EHCI_BAR
-#define EARLY_UART_BAR CONFIG_TTYS0_BASE
-#define EARLY_TEMP_MMIO 0xfed08000
-
#endif
diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c
index 48800ededa..c8fbfcadf7 100644
--- a/src/soc/intel/broadwell/pei_data.c
+++ b/src/soc/intel/broadwell/pei_data.c
@@ -17,13 +17,13 @@ void broadwell_fill_pei_data(struct pei_data *pei_data)
pei_data->usbdebug = CONFIG(USBDEBUG);
pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
- pei_data->ehcibar = EARLY_EHCI_BAR;
- pei_data->xhcibar = EARLY_XHCI_BAR;
- pei_data->gttbar = EARLY_GTT_BAR;
+ pei_data->ehcibar = CONFIG_EHCI_BAR;
+ pei_data->xhcibar = 0xd7000000;
+ pei_data->gttbar = 0xe0000000;
pei_data->pmbase = ACPI_BASE_ADDRESS;
pei_data->gpiobase = GPIO_BASE_ADDRESS;
pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
- pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
+ pei_data->temp_mmio_base = 0xfed08000;
pei_data->tx_byte = &send_to_console;
pei_data->ddr_refresh_2x = 1;
}