1 files changed, 22 insertions, 20 deletions

diff --git a/src/soc/intel/xeon_sp/iio_ioapic.c b/src/soc/intel/xeon_sp/iio_ioapic.c
index 0b9cb9dc2e..456524a901 100644
--- a/src/soc/intel/xeon_sp/iio_ioapic.c
+++ b/src/soc/intel/xeon_sp/iio_ioapic.c
@@ -1,38 +1,40 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
+#include <arch/ioapic.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
 #include <intelblocks/acpi.h>
-#include <soc/chip_common.h>
 #include <soc/util.h>
+#include <soc/pci_devs.h>
 #include <stdint.h>
 
 static uintptr_t xeonsp_ioapic_bases[CONFIG_MAX_SOCKET * MAX_IIO_STACK + 1];
 
 size_t soc_get_ioapic_info(const uintptr_t *ioapic_bases[])
 {
+	struct device *dev = NULL;
 	int index = 0;
-	const IIO_UDS *hob = get_iio_uds();
 
 	*ioapic_bases = xeonsp_ioapic_bases;
 
-	for (int socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
-		if (!soc_cpu_is_enabled(socket))
+	/*
+	 * Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
+	 * The IIO IOAPIC is placed at 0x1000 from the reported base.
+	 */
+	xeonsp_ioapic_bases[index++] = IO_APIC_ADDR;
+
+	while ((dev = dev_find_class(PCI_CLASS_SYSTEM_PIC << 8, dev))) {
+		if (!is_pci_ioapic(dev))
+			continue;
+
+		u16 abar = pci_read_config16(dev, APIC_ABAR);
+		if (!abar)
 			continue;
-		for (int stack = 0; stack < MAX_IIO_STACK; ++stack) {
-			const STACK_RES *ri =
-				&hob->PlatformData.IIO_resource[socket].StackRes[stack];
-			uint32_t ioapic_base = ri->IoApicBase;
-			if (ioapic_base == 0 || ioapic_base == 0xFFFFFFFF)
-				continue;
-			xeonsp_ioapic_bases[index++] = ioapic_base;
-			/*
-			 * Stack 0 has non-PCH IOAPIC and PCH IOAPIC.
-			 * The IIO IOAPIC is placed at 0x1000 from the reported base.
-			 */
-			if (socket == 0 && stack == 0) {
-				ioapic_base += 0x1000;
-				xeonsp_ioapic_bases[index++] = ioapic_base;
-			}
-		}
+		const u32 addr = IO_APIC_ADDR | ((abar & 0xfff) << 8);
+
+		printk(BIOS_DEBUG, "%s: %s: IOAPIC Address: 0x%x\n",
+		       __func__, dev_path(dev), addr);
+		xeonsp_ioapic_bases[index++] = addr;
 	}
 
 	return index;