diff options
Diffstat (limited to 'src/soc/intel/xeon_sp/ibl/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/ibl/include/soc/pmc.h | 15 |
3 files changed, 0 insertions, 27 deletions
diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h b/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h deleted file mode 100644 index 911ff15203..0000000000 --- a/src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DEVICE_AZALIA_H -#define DEVICE_AZALIA_H - -#define HDA_PCS 0x54 -#define HDA_PCS_PS_D3HOT 3 - -#endif /* DEVICE_AZALIA_H */ diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h index f4276c9de6..73b12b35a0 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/pcr_ids.h @@ -5,11 +5,8 @@ #define PID_NOT_SUPPORTED 0xff #define PID_ITSS 0x00 -#define PID_IOTRAP 0x01 #define PID_RTC PID_NOT_SUPPORTED -#define PID_DMI PID_NOT_SUPPORTED #define PID_PSF3 PID_NOT_SUPPORTED -#define PID_ESPI 0x02 #define PID_GPIOCOM0 0x03 #define PID_GPIOCOM5 PID_NOT_SUPPORTED #define PID_GPIOCOM4 PID_NOT_SUPPORTED diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h index 09bfbdbb30..f36435dd2f 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/pmc.h @@ -9,25 +9,17 @@ /* Memory mapped IO registers in PMC */ #define GEN_PMCON_A 0x1020 #define GBL_RST_STS (1 << 24) -#define DISB (1 << 23) #define MS4V (1 << 18) #define SUS_PWR_FLR (1 << 16) #define PWR_FLR (1 << 14) -#define HOST_RST_STS (1 << 9) #define PER_SMI_SEL_MASK (3 << 1) #define SMI_RATE_64S (0 << 1) -#define SMI_RATE_32S (1 << 1) -#define SMI_RATE_16S (2 << 1) -#define SMI_RATE_8S (3 << 1) #define SLEEP_AFTER_POWER_FAIL (1 << 0) #define GEN_PMCON_B 0x1024 #define SLP_STR_POL_LOCK (1 << 18) -#define SMI_LOCK (1 << 4) #define RTC_BATTERY_DEAD (1 << 2) #define PM_CFG 0x1818 #define PMC_LOCK (1 << 27) -#define PMSYNC_MISC_CFG 0x18c8 -#define PMSYNC_LOCK (1 << 15) #define PCH_PWRM_ACPI_TMR_CTL 0x18fc #define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x1920 @@ -35,10 +27,7 @@ #define GPE0_DW_SHIFT(x) (4 * (x)) #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE1 0x1928 -#define ACTL 0x1BD8 #define PMC_ACPI_CNT 0x44 -#define PWRM_EN (1 << 8) -#define ACPI_EN (1 << 7) #define SCI_IRQ_SEL (7 << 0) #define SCI_IRQ_ADJUST 0 #define SCIS_IRQ9 0 @@ -48,9 +37,5 @@ #define SCIS_IRQ21 5 #define SCIS_IRQ22 6 #define SCIS_IRQ23 7 -#define ST_PG_FDIS1 0x1e20 -#define ST_FDIS_LK (1 << 31) -#define NST_PG_FDIS1 0x1e28 -#define NST_FDIS_DSP (1 << 23) #endif |