3 files changed, 99 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/ebg/Makefile.mk b/src/soc/intel/xeon_sp/ebg/Makefile.mk
index ac73acbde9..b05c05bbb3 100644
--- a/src/soc/intel/xeon_sp/ebg/Makefile.mk
+++ b/src/soc/intel/xeon_sp/ebg/Makefile.mk
@@ -2,6 +2,6 @@
 
 bootblock-y += soc_gpio.c soc_pch.c
 romstage-y += soc_gpio.c soc_pmutil.c soc_pch.c
-ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c
+ramstage-y += lockdown.c soc_gpio.c soc_pch.c soc_pmutil.c soc_xhci.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/ebg/include
diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
new file mode 100644
index 0000000000..005a8e1b0b
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ebg/include/soc/xhci.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _XHCI_H_
+#define _XHCI_H_
+
+#include <types.h>
+
+#define USB2_OC_PIN_0 0x90A4
+#define USB2_OC_PIN_1 0x90A8
+#define USB2_OC_PIN_2 0x90AC
+#define USB2_OC_PIN_3 0x90B0
+#define USB2_OC_PIN_4 0x90B4
+#define USB2_OC_PIN_5 0x90B8
+#define USB2_OC_PIN_6 0x90BC
+#define USB2_OC_PIN_7 0x90C0
+
+#define USB3_OC_PIN_0 0x9124
+#define USB3_OC_PIN_1 0x9128
+#define USB3_OC_PIN_2 0x912C
+#define USB3_OC_PIN_3 0x9130
+#define USB3_OC_PIN_4 0x9134
+#define USB3_OC_PIN_5 0x9138
+#define USB3_OC_PIN_6 0x913C
+#define USB3_OC_PIN_7 0x9140
+
+#define USB_PORT_0 BIT(0)
+#define USB_PORT_1 BIT(1)
+#define USB_PORT_2 BIT(2)
+#define USB_PORT_3 BIT(3)
+#define USB_PORT_4 BIT(4)
+#define USB_PORT_5 BIT(5)
+#define USB_PORT_6 BIT(6)
+#define USB_PORT_7 BIT(7)
+#define USB_PORT_8 BIT(8)
+#define USB_PORT_9 BIT(9)
+#define USB_PORT_10 BIT(10)
+#define USB_PORT_11 BIT(11)
+#define USB_PORT_12 BIT(12)
+#define USB_PORT_13 BIT(13)
+#define USB_PORT_14 BIT(14)
+#define USB_PORT_15 BIT(15)
+#define USB_PORT_NONE 0
+#define OCCFGDONE BIT(31)
+
+struct usb_oc_mapping {
+	uint32_t pin;
+	uint32_t port;
+};
+
+void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins);
+void lock_oc_cfg(bool lock);
+
+#endif /* _XHCI_H_ */
diff --git a/src/soc/intel/xeon_sp/ebg/soc_xhci.c b/src/soc/intel/xeon_sp/ebg/soc_xhci.c
new file mode 100644
index 0000000000..f8aa37b88d
--- /dev/null
+++ b/src/soc/intel/xeon_sp/ebg/soc_xhci.c
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <soc/pch_pci_devs.h>
+#include <soc/xhci.h>
+#include <types.h>
+
+// XHCI register
+#define SYS_BUS_CFG2 0x44
+
+static uint8_t *get_xhci_bar(void)
+{
+	const struct resource *res;
+	res = probe_resource(PCH_DEV_XHCI, PCI_BASE_ADDRESS_0);
+	if (!res) {
+		printk(BIOS_ERR, "XHCI BAR is not found\n");
+		return NULL;
+	}
+	return (void *)(uintptr_t)res->base;
+}
+
+void write_usb_oc_mapping(const struct usb_oc_mapping *config, uint8_t pins)
+{
+	uint8_t *mbar = get_xhci_bar();
+	uint8_t i;
+
+	if (mbar == NULL) {
+		printk(BIOS_ERR, "XHCI BAR is invalid, skip USB OC mapping configuration\n");
+		return;
+	}
+	for (i = 0; i < pins; i++)
+		write32(mbar + config[i].pin, config[i].port);
+}
+
+void lock_oc_cfg(bool lock)
+{
+	uint32_t cfg = pci_read_config32(PCH_DEV_XHCI, SYS_BUS_CFG2);
+
+	if (lock)
+		cfg |= OCCFGDONE;
+	else
+		cfg &= ~(OCCFGDONE);
+	pci_write_config32(PCH_DEV_XHCI, SYS_BUS_CFG2, cfg);
+}