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Diffstat (limited to 'src/soc/intel/xeon_sp/cpx')
-rw-r--r--src/soc/intel/xeon_sp/cpx/hob_display.c30
-rw-r--r--src/soc/intel/xeon_sp/cpx/romstage.c2
-rw-r--r--src/soc/intel/xeon_sp/cpx/upd_display.c4
3 files changed, 23 insertions, 13 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c
index 4f13759ad1..d5910c302b 100644
--- a/src/soc/intel/xeon_sp/cpx/hob_display.c
+++ b/src/soc/intel/xeon_sp/cpx/hob_display.c
@@ -142,14 +142,14 @@ void soc_display_iio_universal_data_hob(void)
hob->PlatformData.IIO_resource[s].IoApicBase);
printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n",
hob->PlatformData.IIO_resource[s].IoApicLimit);
- printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem32Base);
- printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem32Limit);
- printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem64Base);
- printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n",
- hob->PlatformData.IIO_resource[s].PciResourceMem64Limit);
+ printk(BIOS_DEBUG, "\tMmio32Base: 0x%x\n",
+ hob->PlatformData.IIO_resource[s].Mmio32Base);
+ printk(BIOS_DEBUG, "\tMmio32Limit: 0x%x\n",
+ hob->PlatformData.IIO_resource[s].Mmio32Limit);
+ printk(BIOS_DEBUG, "\tMmio64Base: 0x%llx\n",
+ hob->PlatformData.IIO_resource[s].Mmio64Base);
+ printk(BIOS_DEBUG, "\tMmio64Limit: 0x%llx\n",
+ hob->PlatformData.IIO_resource[s].Mmio64Limit);
printk(BIOS_DEBUG, "\t============ Stack Info ================\n");
for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
@@ -158,12 +158,22 @@ void soc_display_iio_universal_data_hob(void)
printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality);
printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase);
printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit);
+ printk(BIOS_DEBUG, "\t\tIoBase: 0x%x\n", ri->IoBase);
+ printk(BIOS_DEBUG, "\t\tIoLimit: 0x%x\n", ri->IoLimit);
+ printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
+ printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
+ printk(BIOS_DEBUG, "\t\tMmio32Base: 0x%x\n", ri->Mmio32Base);
+ printk(BIOS_DEBUG, "\t\tMmio32Limit: 0x%x\n", ri->Mmio32Limit);
+ printk(BIOS_DEBUG, "\t\tMmio64Base: 0x%llx\n", ri->Mmio64Base);
+ printk(BIOS_DEBUG, "\t\tMmio64Limit: 0x%llx\n", ri->Mmio64Limit);
+ printk(BIOS_DEBUG, "\t\tPciResourceBusBase: 0x%x\n",
+ ri->PciResourceBusBase);
+ printk(BIOS_DEBUG, "\t\tPciResourceBusLimit: 0x%x\n",
+ ri->PciResourceBusLimit);
printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n",
ri->PciResourceIoBase);
printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n",
ri->PciResourceIoLimit);
- printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
- printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n",
ri->PciResourceMem32Base);
printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n",
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c
index 4b97ddc96d..9952d62d1c 100644
--- a/src/soc/intel/xeon_sp/cpx/romstage.c
+++ b/src/soc/intel/xeon_sp/cpx/romstage.c
@@ -12,7 +12,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
- FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+ FSPM_CONFIG *m_cfg = &mupd->FspmConfig;
FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
/*
diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c
index d3222e65f0..ae5eeda09c 100644
--- a/src/soc/intel/xeon_sp/cpx/upd_display.c
+++ b/src/soc/intel/xeon_sp/cpx/upd_display.c
@@ -12,8 +12,8 @@ void soc_display_fspm_upd_params(
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd)
{
- const FSP_M_CONFIG *new;
- const FSP_M_CONFIG *old;
+ const FSPM_CONFIG *new;
+ const FSPM_CONFIG *old;
old = &fspm_old_upd->FspmConfig;
new = &fspm_new_upd->FspmConfig;