diff options
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/chip.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/chip.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 500f83e41a..34e0e27936 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <console/debug.h> #include <cpu/x86/lapic.h> +#include <cpu/x86/mp.h> #include <device/pci.h> #include <intelblocks/acpi.h> #include <intelblocks/gpio.h> @@ -12,6 +13,7 @@ #include <soc/acpi.h> #include <soc/chip_common.h> #include <soc/cpu.h> +#include <soc/msr.h> #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/p2sb.h> @@ -141,6 +143,22 @@ static void set_pcu_locks(void) } +static void set_msr_locks(void *unused) +{ + /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */ + msr_t msr; + + /* Lock Turbo */ + msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO); + msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK); + wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr); + + /* Lock AES enable */ + msr = rdmsr(MSR_FEATURE_CONFIG); + msr.lo |= FEATURE_CONFIG_LOCK; + wrmsr(MSR_FEATURE_CONFIG, msr); +} + static void chip_final(void *data) { /* Lock SBI */ @@ -157,6 +175,7 @@ static void chip_final(void *data) uint8_t reg8 = pci_io_read_config8(PCI_DEV(0, 0, 0), 0x88); pci_io_write_config8(PCI_DEV(0, 0, 0), 0x88, reg8 | (1 << 4)); + mp_run_on_all_cpus(set_msr_locks, NULL); set_pcu_locks(); p2sb_hide(); |