summaryrefslogtreecommitdiff
path: root/src/soc/intel/xeon_sp/cpx/chip.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/chip.c')
-rw-r--r--src/soc/intel/xeon_sp/cpx/chip.c18
1 files changed, 0 insertions, 18 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 9164b7cbe7..19bf2af7e5 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -14,7 +14,6 @@
#include <soc/acpi.h>
#include <soc/chip_common.h>
#include <soc/cpu.h>
-#include <soc/msr.h>
#include <soc/pch.h>
#include <soc/ramstage.h>
#include <soc/p2sb.h>
@@ -144,22 +143,6 @@ static void set_pcu_locks(void)
}
-static void set_msr_locks(void *unused)
-{
- /* The MSRs and CSRS have the same register layout. Use the CSRS bit definitions */
- msr_t msr;
-
- /* Lock Turbo */
- msr = rdmsr(MSR_TURBO_ACTIVATION_RATIO);
- msr.lo |= (TURBO_ACTIVATION_RATIO_LOCK);
- wrmsr(MSR_TURBO_ACTIVATION_RATIO, msr);
-
- /* Lock AES enable */
- msr = rdmsr(MSR_FEATURE_CONFIG);
- msr.lo |= FEATURE_CONFIG_LOCK;
- wrmsr(MSR_FEATURE_CONFIG, msr);
-}
-
static void set_imc_locks(void)
{
struct device *dev = 0;
@@ -182,7 +165,6 @@ static void chip_final(void *data)
/* LOCK PAM */
pci_or_config32(pcidev_path_on_root(PCI_DEVFN(0, 0)), 0x80, 1 << 0);
- mp_run_on_all_cpus(set_msr_locks, NULL);
set_pcu_locks();
set_imc_locks();
set_upi_locks();