aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/tigerlake/romstage/fsp_params_tgl.c')
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params_tgl.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index 95f637e4ec..32f1b031a9 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -143,8 +143,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
else
m_cfg->TcssItbtPcie3En = 0;
- /* Enable Hyper Threading */
- m_cfg->HyperThreading = 1;
+ /* Hyper Threading */
+ m_cfg->HyperThreading = !config->HyperThreadingDisable;
+
/* Disable Lock PCU Thermal Management registers */
m_cfg->LockPTMregs = 0;
/* Channel Hash Mask:0x0001=BIT6 set(Minimal), 0x3FFF=BIT[19:6] set(Maximum) */