diff options
Diffstat (limited to 'src/soc/intel/tigerlake/acpi/tcss_pcierp.asl')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/tcss_pcierp.asl | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 2d40dc31e4..5ef5dff503 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -1,25 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * The PCI-SIG engineering change requirement provides the ACPI additions for firmware latency - * optimization. Both of FW_RESET_TIME and FW_D3HOT_TO_D0_TIME are applicable to the upstream - * port of the USB4/TBT topology. - */ -/* Number of microseconds to wait after a conventional reset */ -#define FW_RESET_TIME 50000 - -/* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 - -/* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 - -/* Number of microseconds to wait from D3 hot to D0 transition */ -#define FW_D3HOT_TO_D0_TIME 50000 - -/* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 - OperationRegion (PXCS, SystemMemory, BASE(_ADR), 0x800) Field (PXCS, AnyAcc, NoLock, Preserve) { |