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Diffstat (limited to 'src/soc/intel/tigerlake/Kconfig')
-rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 3e080cce60..c6bb167c9f 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -191,9 +191,6 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL hex default 0x7fff -config CHROMEOS - select CHROMEOS_RAMOOPS_DYNAMIC - # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. config TPM_CR50 |