aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/skylake/romstage
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/skylake/romstage')
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index a93407620b..64f9d7d2be 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -186,8 +186,7 @@ asmlinkage void car_stage_entry(void)
}
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf);
}