3 files changed, 7 insertions, 24 deletions
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 52029fcf78..68467b5ab0 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -6,4 +6,4 @@ romstage-y += romstage.c
 romstage-y += smbus.c
 romstage-y += spi.c
 romstage-y += systemagent.c
-romstage-$(CONFIG_INTEL_PCH_UART_CONSOLE) += uart.c
+romstage-y += uart.c
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 4230664911..919b747211 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -50,8 +50,7 @@ void soc_pre_console_init(struct romstage_params *params)
 	/* System Agent Early Initialization */
 	systemagent_early_init();
 
-	if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE))
-		pch_uart_init();
+	pch_uart_init();
 }
 
 /* SOC initialization before RAM is enabled */
diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c
index 8ddcbadda8..8aa1053150 100644
--- a/src/soc/intel/skylake/romstage/uart.c
+++ b/src/soc/intel/skylake/romstage/uart.c
@@ -28,27 +28,10 @@
 
 void pch_uart_init(void)
 {
-	device_t dev;
-	u32 tmp, legacy;
+	device_t dev = PCH_DEV_UART2;
+	u32 tmp;
 	u8 *base = (u8 *)CONFIG_TTYS0_BASE;
 
-	switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) {
-	case 0:
-		dev = PCH_DEV_UART0;
-		legacy = SIO_PCH_LEGACY_UART0;
-		break;
-	case 1:
-		dev = PCH_DEV_UART1;
-		legacy = SIO_PCH_LEGACY_UART1;
-		break;
-	case 2:
-		dev = PCH_DEV_UART2;
-		legacy = SIO_PCH_LEGACY_UART2;
-		break;
-	default:
-		return;
-	}
-
 	/* Set configured UART base address */
 	pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base);
 
@@ -70,6 +53,7 @@ void pch_uart_init(void)
 		(SIO_REG_PPR_CLOCK_M_DIV << 1);
 	write32(base + SIO_REG_PPR_CLOCK, tmp);
 
-	/* Put UART in byte access mode for 16550 compatibility */
-	pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, legacy);
+	/* Put UART2 in byte access mode for 16550 compatibility */
+	pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0,
+		SIO_PCH_LEGACY_UART2);
 }