diff options
| author | Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com> | 2015-07-15 16:02:25 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-07-21 20:10:19 +0200 |
| commit | 5c56ce13f4a81970ed8c9a2987c2ea55376da52d (patch) | |
| tree | ba4508864e22ca5ca14cfa912147081e0fffee28 /src/soc/intel/skylake/romstage | |
| parent | bbbfbf2e0fe3c1af135a955505b6a2fd73681a8e (diff) | |
Skylake: Only support UART2 as debug port, clean up the rest
On Skylake, only UART2 is supported as debug port and the macros
INTEL_PCH_UART_CONSOLE_NUMBER, INTEL_PCH_UART_CONSOLE and the partial
code for UART0, 1 are cleaned up for Skylake and Sklrvp, Kunimitsu and
Glados boards.
BRANCH=none
BUG=chrome-os-partner:40857
TEST=Built for kunimitsu, checked the coreboot logs on LPSS UART2
Change-Id: I2fbcfb1d1ca6f59309a77c67d022cf4f5da7f7c0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e714c18d462bc7bdd7068309fb6be77da6973642
Original-Change-Id: I9343abd90ce685ea2d676047dccbefad7457b69f
Original-Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.ch@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/285793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/10994
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/skylake/romstage')
| -rw-r--r-- | src/soc/intel/skylake/romstage/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/uart.c | 26 |
3 files changed, 7 insertions, 24 deletions
diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 52029fcf78..68467b5ab0 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -6,4 +6,4 @@ romstage-y += romstage.c romstage-y += smbus.c romstage-y += spi.c romstage-y += systemagent.c -romstage-$(CONFIG_INTEL_PCH_UART_CONSOLE) += uart.c +romstage-y += uart.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 4230664911..919b747211 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -50,8 +50,7 @@ void soc_pre_console_init(struct romstage_params *params) /* System Agent Early Initialization */ systemagent_early_init(); - if (IS_ENABLED(CONFIG_INTEL_PCH_UART_CONSOLE)) - pch_uart_init(); + pch_uart_init(); } /* SOC initialization before RAM is enabled */ diff --git a/src/soc/intel/skylake/romstage/uart.c b/src/soc/intel/skylake/romstage/uart.c index 8ddcbadda8..8aa1053150 100644 --- a/src/soc/intel/skylake/romstage/uart.c +++ b/src/soc/intel/skylake/romstage/uart.c @@ -28,27 +28,10 @@ void pch_uart_init(void) { - device_t dev; - u32 tmp, legacy; + device_t dev = PCH_DEV_UART2; + u32 tmp; u8 *base = (u8 *)CONFIG_TTYS0_BASE; - switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { - case 0: - dev = PCH_DEV_UART0; - legacy = SIO_PCH_LEGACY_UART0; - break; - case 1: - dev = PCH_DEV_UART1; - legacy = SIO_PCH_LEGACY_UART1; - break; - case 2: - dev = PCH_DEV_UART2; - legacy = SIO_PCH_LEGACY_UART2; - break; - default: - return; - } - /* Set configured UART base address */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); @@ -70,6 +53,7 @@ void pch_uart_init(void) (SIO_REG_PPR_CLOCK_M_DIV << 1); write32(base + SIO_REG_PPR_CLOCK, tmp); - /* Put UART in byte access mode for 16550 compatibility */ - pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, legacy); + /* Put UART2 in byte access mode for 16550 compatibility */ + pcr_andthenor32(PID_SERIALIO, R_PCH_PCR_SERIAL_IO_GPPRVRW7, 0, + SIO_PCH_LEGACY_UART2); } |