diff options
Diffstat (limited to 'src/soc/intel/skylake/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 91a496eb52..6c5d64a6c6 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_def.h> #include <elog.h> #include <reset.h> @@ -37,6 +38,7 @@ #include <soc/pci_devs.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> +#include <soc/pmc.h> #include <soc/serialio.h> #include <soc/romstage.h> #include <soc/spi.h> @@ -405,3 +407,18 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); soc_display_upd_value("RMT", 1, old->RMT, new->RMT); } + +/* SOC initialization after RAM is enabled. */ +void soc_after_ram_init(struct romstage_params *params) +{ + /* Set the DISB as soon as possible after DRAM + * init and MRC cache is saved. + */ + u32 disb_val = 0; + device_t dev = PCH_DEV_PMC; + disb_val = pci_read_config32(dev, GEN_PMCON_A); + disb_val |= DISB; + /* Preserve bits which get cleared up if written 1 */ + disb_val &= ~(GBL_RST_STS | MS4V); + pci_write_config32(dev, GEN_PMCON_A, disb_val); +} |