1 files changed, 14 insertions, 24 deletions

diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index dee93d889b..1332e2d7cd 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -34,33 +34,22 @@ struct pme_status_info {
 
 #define PME_STS_BIT		(1 << 15)
 
-static void pch_log_add_elog_event(const struct pme_status_info *info)
-{
-	/*
-	 * If wake source is XHCI, check for detailed wake source events on
-	 * USB2/3 ports.
-	 */
-	if ((info->devfn == PCH_DEVFN_XHCI) &&
-			pch_xhci_update_wake_event(soc_get_xhci_usb_info()))
-		return;
-
-	elog_add_event_wake(info->elog_event, 0);
-}
-
 static void pch_log_pme_internal_wake_source(void)
 {
 	size_t i;
 	uint16_t val;
 	bool dev_found = false;
 
-	struct pme_status_info pme_status_info[] = {
+	const struct pme_status_info pme_status_info[] = {
 		{ PCH_DEVFN_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA },
 		{ PCH_DEVFN_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE },
 		{ PCH_DEVFN_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA },
 		{ PCH_DEVFN_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE },
-		{ PCH_DEVFN_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI },
 		{ PCH_DEVFN_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI },
 	};
+	const struct xhci_wake_info xhci_wake_info[] = {
+		{ PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI },
+	};
 
 	for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) {
 		pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(pme_status_info[i].devfn),
@@ -71,19 +60,20 @@ static void pch_log_pme_internal_wake_source(void)
 		if ((val == 0xFFFF) || !(val & PME_STS_BIT))
 			continue;
 
-		pch_log_add_elog_event(&pme_status_info[i]);
+		elog_add_event_wake(pme_status_info[i].elog_event, 0);
 		dev_found = true;
 	}
 
 	/*
-	 * If device is still not found, but the wake source is internal PME,
-	 * try probing XHCI ports to see if any of the USB2/3 ports indicate
-	 * that it was the wake source. This path would be taken in case of GSMI
-	 * logging with S0ix where the pci_pm_resume_noirq runs and clears the
-	 * PME_STS_BIT in controller register.
+	 * Check the XHCI controllers' USB2 & USB3 ports for wake events. There
+	 * are cases (GSMI logging for S0ix clears PME_STS_BIT) where the XHCI
+	 * controller's PME_STS_BIT may have already been cleared, so the host
+	 * controller wake wouldn't get logged here; therefore, the host
+	 * controller wake event is logged before its corresponding port wake
+	 * event is logged.
 	 */
-	if (!dev_found)
-		dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info());
+	dev_found |= xhci_update_wake_event(xhci_wake_info,
+					    ARRAY_SIZE(xhci_wake_info));
 
 	if (!dev_found)
 		elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
@@ -137,7 +127,7 @@ static void pch_log_rp_wake_source(void)
 		 * Linux kernel uses PME STS bit information. So do not clear
 		 * this bit.
 		 */
-		pch_log_add_elog_event(&pme_status_info[i]);
+		elog_add_event_wake(pme_status_info[i].elog_event, 0);
 	}
 }