diff options
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/pci_devs.h | 17 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/reg_access.h | 31 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/romstage.h | 1 |
3 files changed, 47 insertions, 2 deletions
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 67d8d32feb..ff9d65f6ef 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -18,9 +18,8 @@ #ifndef _QUARK_PCI_DEVS_H_ #define _QUARK_PCI_DEVS_H_ -#include <arch/io.h> #include <device/pci.h> -#include <soc/QuarkNcSocId.h> +#include <soc/reg_access.h> /* DEVICE 0 (Memory Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) @@ -29,6 +28,8 @@ #define I2CGPIO_DEVID 0x0934 #define HSUART_DEVID 0x0936 #define EHCI_DEVID 0x0939 +#define PCIE_PORT0_DEVID 0x11c3 +#define PCIE_PORT1_DEVID 0x11c4 /* IO Fabric 1 */ #define SIO1_DEV 0x14 @@ -45,6 +46,18 @@ #define I2CGPIO_DEV_FUNC PCI_DEVFN(I2CGPIO_DEV, I2CGPIO_FUNC) #define I2CGPIO_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, I2CGPIO_DEV, I2CGPIO_FUNC) +/* PCIe Ports */ +#define PCIE_DEV 0x17 +#define PCIE_PORT0_DEV PCIE_DEV +#define PCIE_PORT0_FUNC 0 +#define PCIE_PORT0_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT0_FUNC) +#define PCIE_PORT0_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT0_FUNC) + +#define PCIE_PORT1_DEV PCIE_DEV +#define PCIE_PORT1_FUNC 1 +#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV,PCIE_PORT1_FUNC) +#define PCIE_PORT1_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, PCIE_DEV, PCIE_PORT1_FUNC) + /* Platform Controller Unit */ #define LPC_DEV PCI_DEVICE_NUMBER_QNC_LPC #define LPC_FUNC PCI_FUNCTION_NUMBER_QNC_LPC diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 66ab7b8621..580400c331 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -16,6 +16,9 @@ #ifndef _QUARK_REG_ACCESS_H_ #define _QUARK_REG_ACCESS_H_ +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> #include <delay.h> #include <fsp/util.h> #include <reg_script.h> @@ -30,6 +33,8 @@ enum { MICROSECOND_DELAY, LEG_GPIO_REGS, GPIO_REGS, + PCIE_AFE_REGS, + PCIE_RESET, }; enum { @@ -83,6 +88,31 @@ enum { #define REG_LEG_GPIO_XOR(reg_, value_) \ REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_) +/* PCIE AFE register access macros */ +#define REG_PCIE_AFE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + PCIE_AFE_REGS) +#define REG_PCIE_AFE_READ(reg_) \ + REG_PCIE_AFE_ACCESS(READ, reg_, 0, 0, 0) +#define REG_PCIE_AFE_WRITE(reg_, value_) \ + REG_PCIE_AFE_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_PCIE_AFE_AND(reg_, value_) \ + REG_PCIE_AFE_RMW(reg_, value_, 0) +#define REG_PCIE_AFE_RMW(reg_, mask_, value_) \ + REG_PCIE_AFE_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_PCIE_AFE_RXW(reg_, mask_, value_) \ + REG_PCIE_AFE_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_PCIE_AFE_OR(reg_, value_) \ + REG_PCIE_AFE_RMW(reg_, 0xffffffff, value_) +#define REG_PCIE_AFE_POLL(reg_, mask_, value_, timeout_) \ + REG_PCIE_AFE_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_PCIE_AFE_XOR(reg_, value_) \ + REG_PCIE_AFE_RXW(reg_, 0xffffffff, value_) + +/* PCIe reset */ +#define MAINBOARD_PCIE_RESET(pin_value_) \ + SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 1, pin_value_, 0, PCIE_RESET) + /* RMU temperature register access macros */ #define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ @@ -152,6 +182,7 @@ enum { void *get_i2c_address(void); void mainboard_gpio_init(void); +void mainboard_gpio_pcie_reset(uint32_t pin_value); void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index c344adac0a..3a9e7a8a2d 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -29,5 +29,6 @@ uint32_t port_reg_read(uint8_t port, uint32_t offset); void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); +void pcie_init(void); #endif /* _QUARK_ROMSTAGE_H_ */ |