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-rw-r--r--src/soc/intel/jasperlake/fsp_params.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index 4ec9294fac..d68494f290 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -5,6 +5,7 @@
#include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
+#include <option.h>
#include <intelblocks/lpss.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/xdci.h>
@@ -14,6 +15,7 @@
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
#include <string.h>
+#include <types.h>
/*
* ME End of Post configuration
@@ -84,7 +86,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->EndOfPostMessage = EOP_DISABLE;
/* Legacy 8254 timer support */
- params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
+ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
+ params->Enable8254ClockGating = !use_8254;
params->Enable8254ClockGatingOnS3 = 1;
/* disable Legacy PME */