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-rw-r--r--src/soc/intel/fsp_baytrail/fsp/Makefile.inc22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_baytrail/fsp/Makefile.inc b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
new file mode 100644
index 0000000000..ebdc80a721
--- /dev/null
+++ b/src/soc/intel/fsp_baytrail/fsp/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2014 Sage Electronic Engineering, LLC.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+ramstage-y += chipset_fsp_util.c
+romstage-y += chipset_fsp_util.c
+