diff options
Diffstat (limited to 'src/soc/intel/fsp_baytrail/baytrail/gpio.h')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/baytrail/gpio.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/fsp_baytrail/baytrail/gpio.h b/src/soc/intel/fsp_baytrail/baytrail/gpio.h index e06c8d6bee..bdbb4a56dc 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/gpio.h +++ b/src/soc/intel/fsp_baytrail/baytrail/gpio.h @@ -300,7 +300,7 @@ #define GPSSUS_GPIO_F1_RANGE_START 11 #define GPSSUS_GPIO_F1_RANGE_END 21 -#ifndef __BOOT_BLOCK__ +#ifndef __BOOTBLOCK__ struct soc_gpio_map { u32 pad_conf0; @@ -344,7 +344,7 @@ uint8_t read_ssus_gpio(uint8_t gpio_num); void configure_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val); -#endif /* #ifndef __BOOT_BLOCK__ */ +#endif /* #ifndef __BOOTBLOCK__ */ /* Functions / defines for changing GPIOs in romstage */ /* SCORE Pad definitions. */ @@ -385,7 +385,7 @@ static inline void ssus_select_func(int pad, int func) write32(pconf0_addr, reg); } -#ifndef __BOOT_BLOCK__ +#ifndef __BOOTBLOCK__ /* These functions require that the input pad be configured as an input GPIO */ static inline int score_get_gpio(int pad) @@ -408,6 +408,6 @@ static inline void ssus_disable_internal_pull(int pad) write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); } -#endif /* #ifndef __BOOT_BLOCK__ */ +#endif /* #ifndef __BOOTBLOCK__ */ #endif /* _BAYTRAIL_GPIO_H_ */ |