diff options
Diffstat (limited to 'src/soc/intel/denverton_ns/smm.c')
| -rw-r--r-- | src/soc/intel/denverton_ns/smm.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/soc/intel/denverton_ns/smm.c b/src/soc/intel/denverton_ns/smm.c index 65d249911a..9d3fa75a6a 100644 --- a/src/soc/intel/denverton_ns/smm.c +++ b/src/soc/intel/denverton_ns/smm.c @@ -23,7 +23,6 @@ #include <cpu/x86/smm.h> #include <string.h> -#include <intelblocks/pmclib.h> #include <soc/iomap.h> #include <soc/soc_util.h> #include <soc/pm.h> @@ -49,10 +48,10 @@ void southcluster_smm_clear_state(void) } /* Dump and clear status registers */ - pmc_clear_smi_status(); - pmc_clear_pm1_status(); - pmc_clear_tco_status(); - pmc_clear_all_gpe_status(); + clear_smi_status(); + clear_pm1_status(); + clear_tco_status(); + clear_gpe_status(); clear_pmc_status(); } @@ -61,8 +60,8 @@ void southcluster_smm_enable_smi(void) printk(BIOS_DEBUG, "Enabling SMIs.\n"); /* Configure events Disable pcie wake. */ - pmc_enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); - pmc_disable_std_gpe(PME_B0_EN); + enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); + disable_gpe(PME_B0_EN); /* Enable SMI generation: * - on APMC writes (io 0xb2) @@ -72,7 +71,7 @@ void southcluster_smm_enable_smi(void) * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - pmc_enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1) |