3 files changed, 16 insertions, 7 deletions

diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h
index 29b231f10d..a7548d40a3 100644
--- a/src/soc/intel/denverton_ns/include/soc/iomap.h
+++ b/src/soc/intel/denverton_ns/include/soc/iomap.h
@@ -29,6 +29,7 @@
 /* Southbridge internal device IO BARs (Set to match FSP settings) */
 #define DEFAULT_PMBASE 0x1800
 #define DEFAULT_ACPI_BASE DEFAULT_PMBASE
+#define ACPI_BASE_ADDRESS DEFAULT_PMBASE
 #define DEFAULT_TCO_BASE 0x400
 
 /* Southbridge internal device MEM BARs (Set to match FSP settings) */
diff --git a/src/soc/intel/denverton_ns/include/soc/pm.h b/src/soc/intel/denverton_ns/include/soc/pm.h
index 2dc8781804..32d8a76793 100644
--- a/src/soc/intel/denverton_ns/include/soc/pm.h
+++ b/src/soc/intel/denverton_ns/include/soc/pm.h
@@ -20,10 +20,9 @@
 
 #include <arch/io.h>
 #include <soc/pmc.h>
+#include <arch/acpi.h>
 
-#define SLEEP_STATE_S0 0
-#define SLEEP_STATE_S3 3
-#define SLEEP_STATE_S5 5
+#define GPE_MAX 127
 
 struct chipset_power_state {
 	uint16_t pm1_sts;
@@ -31,8 +30,8 @@ struct chipset_power_state {
 	uint32_t pm1_cnt;
 	uint16_t tco1_sts;
 	uint16_t tco2_sts;
-	uint32_t gpe0_sts[4];
-	uint32_t gpe0_en[4];
+	uint32_t gpe0_sts[GPE0_REG_MAX];
+	uint32_t gpe0_en[GPE0_REG_MAX];
 	uint32_t gen_pmcon_a;
 	uint32_t gen_pmcon_b;
 	uint32_t gblrst_cause[2];
diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h
index edb5c55df6..4db3981d79 100644
--- a/src/soc/intel/denverton_ns/include/soc/pmc.h
+++ b/src/soc/intel/denverton_ns/include/soc/pmc.h
@@ -120,7 +120,10 @@
 #define GPE_CTRL 0x40
 #define SWGPE_CTRL	(1 << 17)
 #define PM2_CNT 0x50
-#define GPE0_STS 0x80
+#define GPE0_REG_MAX		4
+#define GPE0_REG_SIZE		32
+#define GPE0_STS(x) (0x80 + (x * 4))
+#define  GPE_STD 0
 #define GPIO31_STS (1 << 31)
 #define GPIO30_STS (1 << 30)
 #define GPIO29_STS (1 << 29)
@@ -166,7 +169,7 @@
 #define IE_SCI_STS (1 << 3)
 #define SWGPE_STS (1 << 2)
 #define HOT_PLUG_STS (1 << 1)
-#define GPE0_EN 0x90
+#define GPE0_EN(x) (0x90 + (x * 4))
 #define GPIO31_EN (1 << 31)
 #define GPIO30_EN (1 << 30)
 #define GPIO29_EN (1 << 29)
@@ -236,6 +239,12 @@
 #define TCO2_CNT 0x0a
 #define TCO_TMR 0x12
 
+/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
+#define PRSTS			0x10
+#define GPIO_GPE_CFG		0x120
+#define  GPE0_DWX_MASK		0x7
+#define GPE0_DW_SHIFT(x)	(4 + 4*(x))
+
 /* I/O ports */
 #define RST_CNT 0xcf9
 #define FULL_RST (1 << 3)