diff options
Diffstat (limited to 'src/soc/intel/denverton_ns/Kconfig')
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 09c140820a..4c0c998792 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -15,17 +15,20 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_X86 select BOOT_DEVICE_SUPPORTS_WRITES + select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select DEBUG_GPIO - select SOC_INTEL_COMMON - select SOC_INTEL_COMMON_RESET - select PLATFORM_USES_FSP2_0 + select FSP_M_XIP + select FSP_T_XIP if FSP_CAR select HAVE_INTEL_FSP_REPO select HAVE_SMI_HANDLER - select CACHE_MRC_SETTINGS - select PCR_COMMON_IOSF_1_0 - select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE + select PCR_COMMON_IOSF_1_0 + select PLATFORM_USES_FSP2_0 + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_ACPI @@ -35,16 +38,15 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_SMBUS + select SUPPORT_CPU_UCODE_IN_CBFS select SOUTHBRIDGE_INTEL_COMMON_SMBUS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING - select CPU_INTEL_COMMON - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE - select SUPPORT_CPU_UCODE_IN_CBFS - select FSP_T_XIP if FSP_CAR - select FSP_M_XIP + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 |