diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/xhci.h | 28 | ||||
| -rw-r--r-- | src/soc/intel/common/block/xhci/Kconfig | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/xhci/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/soc/intel/common/block/xhci/elog.c | 155 |
4 files changed, 194 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 32ae9a2a05..86b598fda1 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -16,6 +16,34 @@ #ifndef SOC_INTEL_COMMON_BLOCK_XHCI_H #define SOC_INTEL_COMMON_BLOCK_XHCI_H +#include <device/device.h> + +/** + * struct xhci_usb_info - Data containing number of USB ports & offset. + * @usb2_port_status_reg: Offset to USB2 port status register. + * @num_usb2_ports: Number of USB2 ports. + * @usb3_port_status_reg: Offset to USB3 port status register. + * @num_usb3_ports: Number of USB3 ports. + */ +struct xhci_usb_info { + uint32_t usb2_port_status_reg; + uint32_t num_usb2_ports; + uint32_t usb3_port_status_reg; + uint32_t num_usb3_ports; +}; + +/** + * pch_xhci_update_wake_event() - Identify and log XHCI wake events. + * @info: Information about number of USB ports and their status reg offset. + * + * This function goes through individual USB port status registers within the + * XHCI block and identifies if any of those USB ports triggered a wake-up and + * log information about those ports to the event log. + * + * Return: True if any port is identified as a wake source, false if none. + */ +bool pch_xhci_update_wake_event(const struct xhci_usb_info *info); + void soc_xhci_init(struct device *dev); #endif /* SOC_INTEL_COMMON_BLOCK_XHCI_H */ diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig index c8fd5fdbd1..59536bac0f 100644 --- a/src/soc/intel/common/block/xhci/Kconfig +++ b/src/soc/intel/common/block/xhci/Kconfig @@ -2,3 +2,11 @@ config SOC_INTEL_COMMON_BLOCK_XHCI bool help Intel Processor common XHCI support + +config SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + bool + default n + depends on SOC_INTEL_COMMON_BLOCK_XHCI + help + Set this option to identify if XHCI caused a wake up and log that + information into the event log. diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc index 43bdf1b29f..d1c505e2a4 100644 --- a/src/soc/intel/common/block/xhci/Makefile.inc +++ b/src/soc/intel/common/block/xhci/Makefile.inc @@ -1 +1,4 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI) += xhci.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG) += elog.c + +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG) += elog.c diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c new file mode 100644 index 0000000000..0fd41bfdf0 --- /dev/null +++ b/src/soc/intel/common/block/xhci/elog.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <intelblocks/xhci.h> +#include <soc/pci_devs.h> +#include <stdint.h> + +/* Wake on disconnect enable */ +#define XHCI_STATUS_WDE (1 << 26) +/* Wake on connect enable */ +#define XHCI_STATUS_WCE (1 << 25) +/* Port link status change */ +#define XHCI_STATUS_PLC (1 << 22) +/* Connect status change */ +#define XHCI_STATUS_CSC (1 << 17) +/* Port link status */ +#define XHCI_STATUS_PLS_SHIFT (5) +#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT) +#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT) + +static bool pch_xhci_csc_set(uint32_t port_status) +{ + return !!(port_status & XHCI_STATUS_CSC); +} + +static bool pch_xhci_wake_capable(uint32_t port_status) +{ + return !!((port_status & XHCI_STATUS_WCE) | + (port_status & XHCI_STATUS_WDE)); +} + +static bool pch_xhci_plc_set(uint32_t port_status) +{ + return !!(port_status & XHCI_STATUS_PLC); +} + +static bool pch_xhci_resume(uint32_t port_status) +{ + return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME; +} + +/* + * Check if a particular USB port caused wake by: + * 1. Change in connect/disconnect status (if enabled) + * 2. USB device activity + * + * Params: + * base : MMIO address of first port. + * num : Number of ports. + * event : Event that needs to be added in case wake source is found. + * + * Return value: + * true : Wake source was found. + * false : Wake source was not found. + */ +static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event) +{ + uint32_t i, port_status; + bool found = false; + + for (i = 0; i < num; i++, base += 0x10) { + /* Read port status and control register for the port. */ + port_status = read32((void *)base); + + /* Ensure that the status is not all 1s. */ + if (port_status == 0xffffffff) + continue; + + /* + * Check if CSC bit is set and port is capable of wake on + * connect/disconnect to identify if the port caused wake + * event for usb attach/detach. + */ + if (pch_xhci_csc_set(port_status) && + pch_xhci_wake_capable(port_status)) { + elog_add_event_wake(event, i + 1); + found = true; + continue; + } + + /* + * Check if PLC is set and PLS indicates resume to identify if + * the port caused wake event for usb activity. + */ + if (pch_xhci_plc_set(port_status) && + pch_xhci_resume(port_status)) { + elog_add_event_wake(event, i + 1); + found = true; + } + } + return found; +} + +/* + * Update elog event and instance depending upon the USB2 port that caused + * the wake event. + * + * Return value: + * true = Indicates that USB2 wake event was found. + * false = Indicates that USB2 wake event was not found. + */ +static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base, + const struct xhci_usb_info *info) +{ + return pch_xhci_port_wake_check(mmio_base + info->usb2_port_status_reg, + info->num_usb2_ports, + ELOG_WAKE_SOURCE_PME_XHCI_USB_2); +} + +/* + * Update elog event and instance depending upon the USB3 port that caused + * the wake event. + * + * Return value: + * true = Indicates that USB3 wake event was found. + * false = Indicates that USB3 wake event was not found. + */ +static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base, + const struct xhci_usb_info *info) +{ + return pch_xhci_port_wake_check(mmio_base + info->usb3_port_status_reg, + info->num_usb3_ports, + ELOG_WAKE_SOURCE_PME_XHCI_USB_3); +} + +bool pch_xhci_update_wake_event(const struct xhci_usb_info *info) +{ + uintptr_t mmio_base; + bool event_found = false; + mmio_base = ALIGN_DOWN(pci_read_config32(PCH_DEV_XHCI, + PCI_BASE_ADDRESS_0), 16); + + if (pch_xhci_usb2_update_wake_event(mmio_base, info)) + event_found = true; + + if (pch_xhci_usb3_update_wake_event(mmio_base, info)) + event_found = true; + + return event_found; +} |