diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/acpi.h | 36 | ||||
| -rw-r--r-- | src/soc/intel/common/acpi/acpi_wake_source.asl | 36 | ||||
| -rw-r--r-- | src/soc/intel/common/acpi_wake_source.c | 90 |
5 files changed, 167 insertions, 0 deletions
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 8e632bb8e5..43c52b5478 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -69,4 +69,8 @@ config ROMSTAGE_RAM_STACK_SIZE default 0x5000 depends on SOC_INTEL_COMMON_STACK +config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 892ae9597d..ade5456bf6 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-$(CONFIG_SOC_INTEL_COMMON_STAGE_CACHE) += stage_cache.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += util.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c # Create and add the MRC cache to the cbfs image ifneq ($(CONFIG_CHROMEOS),y) diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h new file mode 100644 index 0000000000..8ee81a641d --- /dev/null +++ b/src/soc/intel/common/acpi.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _INTEL_COMMON_ACPI_H_ +#define _INTEL_COMMON_ACPI_H_ + +#include <stdint.h> + +/* + * SOC specific handler to provide the wake source data for ACPI _SWS. + * + * @pm1: PM1_STS register with only enabled events set + * @gpe0: GPE0_STS registers with only enabled events set + * + * return the number of registers in the gpe0 array or -1 if nothing + * is provided by this function. + */ +int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); + +#endif diff --git a/src/soc/intel/common/acpi/acpi_wake_source.asl b/src/soc/intel/common/acpi/acpi_wake_source.asl new file mode 100644 index 0000000000..30e70d9e55 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi_wake_source.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Scope (\_SB) +{ + Method (_SWS) + { + /* Index into PM1 for device that caused wake */ + Return (\PM1I) + } +} + +Scope (\_GPE) +{ + Method (_SWS) + { + /* Index into GPE for device that caused wake */ + Return (\GPEI) + } +} diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c new file mode 100644 index 0000000000..43d6b03b2b --- /dev/null +++ b/src/soc/intel/common/acpi_wake_source.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/acpi.h> +#include <bootstate.h> +#include <cbmem.h> +#include <console/console.h> +#include <soc/nvs.h> +#include <stdint.h> +#include <stdlib.h> +#include "acpi.h" + +__attribute__((weak)) int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) +{ + return -1; +} + +/* Save wake source data for ACPI _SWS methods in NVS */ +static void acpi_save_wake_source(void *unused) +{ + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + uint32_t pm1, *gpe0; + int gpe_reg, gpe_reg_count; + int reg_size = sizeof(uint32_t) * 8; + + if (!gnvs) + return; + + gnvs->pm1i = -1; + gnvs->gpei = -1; + + gpe_reg_count = soc_fill_acpi_wake(&pm1, &gpe0); + if (gpe_reg_count < 0) + return; + + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < reg_size; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + /* Scan for first set bit in GPE registers */ + for (gpe_reg = 0; gpe_reg < gpe_reg_count; gpe_reg++) { + uint32_t gpe = gpe0[gpe_reg]; + int start = gpe_reg * reg_size; + int end = start + reg_size; + + if (gpe == 0) { + if (!gnvs->gpei) + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= gpe_reg_count * reg_size) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", + (long long)gnvs->pm1i, (long long)gnvs->gpei); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, acpi_save_wake_source, NULL); |