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Diffstat (limited to 'src/soc/intel/common')
-rw-r--r--src/soc/intel/common/block/include/intelblocks/uart.h8
-rw-r--r--src/soc/intel/common/block/uart/Kconfig12
-rw-r--r--src/soc/intel/common/block/uart/uart.c18
3 files changed, 30 insertions, 8 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h
index b46edd76d7..9ec5004e08 100644
--- a/src/soc/intel/common/block/include/intelblocks/uart.h
+++ b/src/soc/intel/common/block/include/intelblocks/uart.h
@@ -19,8 +19,12 @@
#include <arch/io.h>
#include <device/device.h>
-void uart_common_init(device_t dev, uintptr_t baseaddr,
- uint32_t clk_m_val, uint32_t clk_n_val);
+/*
+ * Common routine to initialize UART controller PCI config space, take it out of
+ * reset and configure M/N dividers.
+ */
+void uart_common_init(device_t dev, uintptr_t baseaddr);
+
void pch_uart_read_resources(struct device *dev);
diff --git a/src/soc/intel/common/block/uart/Kconfig b/src/soc/intel/common/block/uart/Kconfig
index 103659f4c4..f4a0e4e4b9 100644
--- a/src/soc/intel/common/block/uart/Kconfig
+++ b/src/soc/intel/common/block/uart/Kconfig
@@ -3,3 +3,15 @@ config SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_LPSS
help
Intel Processor common UART support
+
+config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL
+ depends on SOC_INTEL_COMMON_BLOCK_UART
+ hex
+ help
+ Clock m-divisor value for m/n divider
+
+config SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL
+ depends on SOC_INTEL_COMMON_BLOCK_UART
+ hex
+ help
+ Clock m-divisor value for m/n divider
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index e8f1bc8094..be30464b13 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -19,8 +19,17 @@
#include <intelblocks/lpss.h>
#include <intelblocks/uart.h>
-void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
- uint32_t clk_n_val)
+static void uart_lpss_init(uintptr_t baseaddr)
+{
+ /* Take UART out of reset */
+ lpss_reset_release(baseaddr);
+
+ /* Set M and N divisor inputs and enable clock */
+ lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,
+ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
+}
+
+void uart_common_init(device_t dev, uintptr_t baseaddr)
{
/* Set UART base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
@@ -29,11 +38,8 @@ void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
pci_write_config32(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- /* Take UART out of reset */
- lpss_reset_release(baseaddr);
+ uart_lpss_init(baseaddr);
- /* Set M and N divisor inputs and enable clock */
- lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
}
#if ENV_RAMSTAGE