diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/pcie/rtd3/rtd3.c | 84 |
1 files changed, 79 insertions, 5 deletions
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 816df05b57..507c3c8dea 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -9,6 +9,8 @@ #include <device/pci.h> #include <intelblocks/pmc.h> #include <intelblocks/pmc_ipc.h> +#include <intelblocks/pcie_rp.h> +#include <soc/iomap.h> #include "chip.h" /* @@ -42,6 +44,14 @@ #define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ #define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ +/* ACPI path to the mutex that protects accesses to PMC ModPhy power gating registers */ +#define RTD3_MUTEX_PATH "\\_SB.PCI0.R3MX" + +enum modphy_pg_state { + PG_DISABLE = 0, + PG_ENABLE = 1, +}; + /* Called from _ON to get PCIe link back to active state. */ static void pcie_rtd3_acpi_l23_exit(void) { @@ -74,12 +84,33 @@ static void pcie_rtd3_acpi_l23_entry(void) acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); } +/* Called from _ON/_OFF to disable/enable ModPHY power gating */ +static void pcie_rtd3_enable_modphy_pg(unsigned int pcie_rp, enum modphy_pg_state state) +{ + /* Enter the critical section */ + acpigen_emit_ext_op(ACQUIRE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); + acpigen_emit_word(ACPI_MUTEX_NO_TIMEOUT); + + acpigen_write_store_int_to_namestr(state, "EMPG"); + acpigen_write_delay_until_namestr_int(100, "AMPG", state); + + /* Exit the critical section */ + acpigen_emit_ext_op(RELEASE_OP); + acpigen_emit_namestring(RTD3_MUTEX_PATH); +} + static void pcie_rtd3_acpi_method_on(unsigned int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) + const struct soc_intel_common_block_pcie_rtd3_config *config, + enum pcie_rp_type rp_type) { acpigen_write_method_serialized("_ON", 0); + /* Disable modPHY power gating for PCH RPs. */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_DISABLE); + /* Assert enable GPIO to turn on device power. */ if (config->enable_gpio.pin_count) { acpigen_enable_tx_gpio(&config->enable_gpio); @@ -98,7 +129,7 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, acpigen_write_sleep(config->reset_delay_ms); } - /* Trigger L23 ready exit flow unless disabld by config. */ + /* Trigger L23 ready exit flow unless disabled by config. */ if (!config->disable_l23) pcie_rtd3_acpi_l23_exit(); @@ -107,7 +138,8 @@ pcie_rtd3_acpi_method_on(unsigned int pcie_rp, static void pcie_rtd3_acpi_method_off(int pcie_rp, - const struct soc_intel_common_block_pcie_rtd3_config *config) + const struct soc_intel_common_block_pcie_rtd3_config *config, + enum pcie_rp_type rp_type) { acpigen_write_method_serialized("_OFF", 0); @@ -122,6 +154,10 @@ pcie_rtd3_acpi_method_off(int pcie_rp, acpigen_write_sleep(config->reset_off_delay_ms); } + /* Enable modPHY power gating for PCH RPs */ + if (rp_type == PCIE_RP_PCH) + pcie_rtd3_enable_modphy_pg(pcie_rp, PG_ENABLE); + /* Disable SRCCLK for this root port if pin is defined. */ if (config->srcclk_pin >= 0) pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); @@ -165,8 +201,31 @@ pcie_rtd3_acpi_method_status(int pcie_rp, acpigen_pop_len(); /* Method */ } +static void write_modphy_opregion(unsigned int pcie_rp) +{ + /* The register containing the Power Gate enable sequence bits is at + PCH_PWRM_BASE + 0x10D0, and the bits to check for sequence completion are at + PCH_PWRM_BASE + 0x10D4. */ + const struct opregion opregion = OPREGION("PMCP", SYSTEMMEMORY, + PCH_PWRM_BASE_ADDRESS + 0x1000, 0xff); + const struct fieldlist fieldlist[] = { + FIELDLIST_OFFSET(0xD0), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("EMPG", 1), /* Enable ModPHY Power Gate */ + FIELDLIST_OFFSET(0xD4), + FIELDLIST_RESERVED(pcie_rp), + FIELDLIST_NAMESTR("AMPG", 1), /* Is ModPHY Power Gate active? */ + }; + + acpigen_write_opregion(&opregion); + acpigen_write_field("PMCP", fieldlist, ARRAY_SIZE(fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); +} + static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) { + static bool mutex_created = false; + const struct soc_intel_common_block_pcie_rtd3_config *config = config_of(dev); static const char *const power_res_states[] = {"_PR0"}; const struct device *parent = dev->bus->dev; @@ -206,6 +265,8 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) return; } + const enum pcie_rp_type rp_type = soc_get_pcie_rp_type(parent); + /* Read port number of root port that this device is attached to. */ pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { @@ -218,21 +279,34 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), config->desc ?: dev->chip_ops->name); + /* Create a mutex for exclusive access to the PMC registers. */ + if (rp_type == PCIE_RP_PCH && !mutex_created) { + acpigen_write_scope("\\_SB.PCI0"); + acpigen_write_mutex("R3MX", 0); + acpigen_write_scope_end(); + mutex_created = true; + } + /* The RTD3 power resource is added to the root port, not the device. */ acpigen_write_scope(scope); if (config->desc) acpigen_write_name_string("_DDN", config->desc); + /* Create OpRegions for MMIO accesses. */ acpigen_write_opregion(&opregion); acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist), FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + /* Create the OpRegion to access the ModPHY PG registers (PCH RPs only) */ + if (rp_type == PCIE_RP_PCH) + write_modphy_opregion(pcie_rp); + /* ACPI Power Resource for controlling the attached device power. */ acpigen_write_power_res("RTD3", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); pcie_rtd3_acpi_method_status(pcie_rp, config); - pcie_rtd3_acpi_method_on(pcie_rp, config); - pcie_rtd3_acpi_method_off(pcie_rp, config); + pcie_rtd3_acpi_method_on(pcie_rp, config, rp_type); + pcie_rtd3_acpi_method_off(pcie_rp, config, rp_type); acpigen_pop_len(); /* PowerResource */ /* Indicate to the OS that device supports hotplug in D3. */ |