diff options
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/thermal.h | 23 | ||||
| -rw-r--r-- | src/soc/intel/common/block/thermal/Kconfig | 10 | ||||
| -rw-r--r-- | src/soc/intel/common/block/thermal/Makefile.inc | 6 | ||||
| -rw-r--r-- | src/soc/intel/common/block/thermal/thermal_common.c | 29 | ||||
| -rw-r--r-- | src/soc/intel/common/block/thermal/thermal_pci.c (renamed from src/soc/intel/common/block/thermal/thermal.c) | 30 | ||||
| -rw-r--r-- | src/soc/intel/common/block/thermal/thermal_pmc.c | 37 |
6 files changed, 67 insertions, 68 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/thermal.h b/src/soc/intel/common/block/include/intelblocks/thermal.h index aa3318c7c4..d995cc7551 100644 --- a/src/soc/intel/common/block/include/intelblocks/thermal.h +++ b/src/soc/intel/common/block/include/intelblocks/thermal.h @@ -3,6 +3,25 @@ #ifndef _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ #define _SOC_INTEL_COMMON_BLOCK_THERMAL_H_ +#define MAX_TRIP_TEMP 205 +/* This is the safest default Trip Temp value */ +#define DEFAULT_TRIP_TEMP 50 + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) + /* Trip Point Temp = (LTT / 2 - 50 degree C) */ + #define GET_LTT_VALUE(x) (((x) + 50) * (2)) +#elif CONFIG(SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) + /* + * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L + * T2L = Bit 28:20 + * T1L = Bit 18:10 + * T0L = Bit 8:0 + */ + #define GET_LTT_VALUE(x) (((x) + 10) << 20 | ((x) + 5) << 10 | (x)) +#else + #error <Undefined: GET_LTT_VALUE macro> +#endif + /* Catastrophic Trip Point Enable */ #define PMC_PWRM_THERMAL_CTEN 0x150c /* Policy Lock-Down Bit */ @@ -30,6 +49,10 @@ /* PHL Lock */ #define PMC_PWRM_THERMAL_PHLC_PHLCLOCK (1 << 31) +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void); +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void); /* Enable thermal sensor power management */ void pch_thermal_configuration(void); diff --git a/src/soc/intel/common/block/thermal/Kconfig b/src/soc/intel/common/block/thermal/Kconfig index b39c74ca0f..7ab72405f0 100644 --- a/src/soc/intel/common/block/thermal/Kconfig +++ b/src/soc/intel/common/block/thermal/Kconfig @@ -4,9 +4,19 @@ config SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers for supported PCH. +config SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV + bool + default n + select SOC_INTEL_COMMON_BLOCK_THERMAL + help + This option allows to configure PCH thermal registers using Thermal PCI device + for chipsets till Ice Lake PCH. + config SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC bool default n + depends on !SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV + select SOC_INTEL_COMMON_BLOCK_THERMAL help This option allows to configure PCH thermal registers using PMC PWRMBASE for chipsets since Tiger Lake PCH. diff --git a/src/soc/intel/common/block/thermal/Makefile.inc b/src/soc/intel/common/block/thermal/Makefile.inc index 2a652192fc..cd71032ecb 100644 --- a/src/soc/intel/common/block/thermal/Makefile.inc +++ b/src/soc/intel/common/block/thermal/Makefile.inc @@ -1,3 +1,5 @@ -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal_common.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) += thermal_pci.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC) += thermal_pmc.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL) += thermal_common.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV) += thermal_pci.c diff --git a/src/soc/intel/common/block/thermal/thermal_common.c b/src/soc/intel/common/block/thermal/thermal_common.c new file mode 100644 index 0000000000..ba1ab062a6 --- /dev/null +++ b/src/soc/intel/common/block/thermal/thermal_common.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/cfg.h> +#include <intelblocks/thermal.h> + +/* Get PCH Thermal Trip from common chip config */ +uint8_t get_thermal_trip_temp(void) +{ + const struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + return common_config->pch_thermal_trip; +} + +/* PCH Low Temp Threshold (LTT) */ +uint32_t pch_get_ltt_value(void) +{ + uint8_t thermal_config; + + thermal_config = get_thermal_trip_temp(); + if (!thermal_config) + thermal_config = DEFAULT_TRIP_TEMP; + + if (thermal_config > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + return GET_LTT_VALUE(thermal_config); +} diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal_pci.c index 6106c49639..1b9f28a176 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal_pci.c @@ -1,41 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <device/device.h> #include <device/mmio.h> -#include <intelblocks/cfg.h> #include <intelblocks/thermal.h> #include <soc/pci_devs.h> #define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c #define CATASTROPHIC_TRIP_POINT_MASK 0x1ff -#define MAX_TRIP_TEMP 205 -/* This is the safest default Trip Temp value */ -#define DEFAULT_TRIP_TEMP 50 -/* Trip Point Temp = (LTT / 2 - 50 degree C) */ -#define GET_LTT_VALUE(x) (((x) + 50) * (2)) - -static uint8_t get_thermal_trip_temp(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->pch_thermal_trip; -} - -/* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(void) -{ - uint8_t thermal_config; - - thermal_config = get_thermal_trip_temp(); - if (!thermal_config) - thermal_config = DEFAULT_TRIP_TEMP; - - if (thermal_config > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - return GET_LTT_VALUE(thermal_config); -} /* Enable thermal sensor power management */ void pch_thermal_configuration(void) diff --git a/src/soc/intel/common/block/thermal/thermal_pmc.c b/src/soc/intel/common/block/thermal/thermal_pmc.c index d233e9d56b..3525b47ecb 100644 --- a/src/soc/intel/common/block/thermal/thermal_pmc.c +++ b/src/soc/intel/common/block/thermal/thermal_pmc.c @@ -1,46 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/mmio.h> -#include <intelblocks/cfg.h> #include <intelblocks/pmclib.h> #include <intelblocks/thermal.h> -#define MAX_TRIP_TEMP 205 -/* This is the safest default Trip Temp value */ -#define DEFAULT_TRIP_TEMP 50 - -/* - * Trip Point = T2L | T1L | T0L where T2L > T1L > T0L - * T2L = Bit 28:20 - * T1L = Bit 18:10 - * T0L = Bit 8:0 - */ -#define GET_LTT_VALUE(x) ((x + 10) << 20 | (x + 5) << 10 | x) - -static uint8_t get_thermal_trip_temp(void) -{ - const struct soc_intel_common_config *common_config; - common_config = chip_get_common_soc_structure(); - - return common_config->pch_thermal_trip; -} - -/* PCH Low Temp Threshold (LTT) */ -static uint32_t pch_get_ltt_value(void) -{ - uint8_t thermal_config; - - thermal_config = get_thermal_trip_temp(); - if (!thermal_config) - thermal_config = DEFAULT_TRIP_TEMP; - - if (thermal_config > MAX_TRIP_TEMP) - die("Input PCH temp trip is higher than allowed range!"); - - return GET_LTT_VALUE(thermal_config); -} - /* * Thermal configuration has evolved over time. With older platform the * thermal device is sitting over PCI and allow to configure its configuration |