diff options
Diffstat (limited to 'src/soc/intel/common/block/smm')
| -rw-r--r-- | src/soc/intel/common/block/smm/smihandler.c | 42 |
1 files changed, 33 insertions, 9 deletions
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 4677d27943..54f4e41e50 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2017 Intel Corp. + * Copyright (C) 2015-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +44,11 @@ static struct global_nvs_t *gnvs; /* SoC overrides. */ +__weak const struct smm_save_state_ops *get_smm_save_state_ops(void) +{ + return &em64t101_smm_ops; +} + /* Specific SOC SMI handler during ramstage finalize phase */ __weak void smihandler_soc_at_finalize(void) { @@ -55,20 +60,29 @@ __weak int smihandler_soc_disable_busmaster(pci_devfn_t dev) return 1; } -/* SMI handlers that should be serviced in SCI mode too. */ -__weak uint32_t smihandler_soc_get_sci_mask(void) -{ - return 0; /* No valid SCI mask for SMI handler */ -} - /* * Needs to implement the mechanism to know if an illegal attempt * has been made to write to the BIOS area. */ -__weak void smihandler_soc_check_illegal_access( +static void smihandler_soc_check_illegal_access( uint32_t tco_sts) { - return; + if (!((tco_sts & (1 << 8)) && CONFIG(SPI_FLASH_SMM) + && fast_spi_wpd_status())) + return; + + /* + * BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + * + * This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + fast_spi_enable_wp(); } /* Mainboard overrides. */ @@ -472,6 +486,16 @@ void smihandler_southbridge_espi( mainboard_smi_espi_handler(); } +/* SMI handlers that should be serviced in SCI mode too. */ +static uint32_t smihandler_soc_get_sci_mask(void) +{ + uint32_t sci_mask = + SMI_HANDLER_SCI_EN(APM_STS_BIT) | + SMI_HANDLER_SCI_EN(SMI_ON_SLP_EN_STS_BIT); + + return sci_mask; +} + void southbridge_smi_handler(void) { int i; |