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-rw-r--r--src/soc/intel/common/block/include/intelblocks/pcie_rp.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
index dff4d97382..7f7dba6d31 100644
--- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
+++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h
@@ -37,6 +37,9 @@ enum pcie_clk_src_flags {
PCIE_CLK_LAN = (1 << 1),
};
+/* coreboot enums are off-by-1 to allow for no config in devicetree */
+#define UPD_INDEX(upd) (upd - 1)
+
/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */
enum L1_substates_control {
L1_SS_FSP_DEFAULT,