diff options
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcr.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/pcr.h b/src/soc/intel/common/block/include/intelblocks/pcr.h index cfe0015f70..c3af2fddc3 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcr.h +++ b/src/soc/intel/common/block/include/intelblocks/pcr.h @@ -38,6 +38,47 @@ void pcr_or32(uint8_t pid, uint16_t offset, uint32_t ordata); void pcr_or16(uint8_t pid, uint16_t offset, uint16_t ordata); void pcr_or8(uint8_t pid, uint16_t offset, uint8_t ordata); +/* SBI command */ +enum { + MEM_READ = 0, + MEM_WRITE = 1, + PCI_CONFIG_READ = 4, + PCI_CONFIG_WRITE = 5, + PCR_READ = 6, + PCR_WRITE = 7, + GPIO_LOCK_UNLOCK = 13, +}; + +struct pcr_sbi_msg { + uint8_t pid; /* 0x00 - Port ID of the SBI message */ + uint32_t offset; /* 0x01 - Register offset of the SBI message */ + uint8_t opcode; /* 0x05 - Opcode */ + bool is_posted; /* 0x06 - Posted message */ + uint16_t fast_byte_enable; /* 0x07 - First Byte Enable */ + uint16_t bar; /* 0x09 - base address */ + uint16_t fid; /* 0x0B - Function ID */ +}; + + +/* + * API to perform sideband communication + * + * Input: + * struct pcr_sbi_msg + * data - read/write for sbi message + * response - + * 0 - successful + * 1 - unsuccessful + * 2 - powered down + * 3 - multi-cast mixed + * + * Output: + * 0: SBI message is successfully completed + * -1: SBI message failure + */ +int pcr_execute_sideband_msg(struct pcr_sbi_msg *msg, uint32_t *data, + uint8_t *response); + /* Get the starting address of the port's registers. */ void *pcr_reg_address(uint8_t pid, uint16_t offset); #endif /* if !defined(__ACPI__) */ |