1 files changed, 68 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/gspi.h b/src/soc/intel/common/block/include/intelblocks/gspi.h
new file mode 100644
index 0000000000..4e10e25d3e
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/gspi.h
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_COMMON_BLOCK_GSPI_H
+#define SOC_INTEL_COMMON_BLOCK_GSPI_H
+
+#include <spi-generic.h>
+#include <stdint.h>
+
+/* GSPI controller structure to allow SoCs to define bus-controller mapping. */
+extern const struct spi_ctrlr gspi_ctrlr;
+
+struct gspi_cfg {
+	/* Bus speed in MHz. */
+	uint32_t speed_mhz;
+	/* Bus should be enabled prior to ramstage with temporary base. */
+	uint8_t early_init;
+};
+
+/* GSPI controller APIs. */
+void gspi_early_bar_init(void);
+
+/* SoC-callbacks */
+/* Get gspi_config array from SoC. Returns NULL in case of error. */
+const struct gspi_cfg *gspi_get_soc_cfg(void);
+
+/* Get base address for early init of GSPI controllers. */
+uintptr_t gspi_get_soc_early_base(void);
+
+/*
+ * Map given SPI bus number to GSPI bus number.
+ * Return value:
+ *  0 = success
+ * -1 = error
+ */
+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus);
+
+/*
+ * Map given GSPI bus number to devfn.
+ * Return value:
+ * -1 = error
+ * otherwise, devfn(>=0) corresponding to GSPI bus number.
+ */
+int gspi_soc_bus_to_devfn(unsigned int gspi_bus);
+
+/*
+ * SoC-provided callback for getting configuration of SPI bus. Driver provides
+ * weak implementation with default SPI-bus configuration.
+ *
+ * Return value:
+ * 0 = Success
+ * -1 = Error
+ */
+int gspi_get_soc_spi_cfg(unsigned int bus, struct spi_cfg *cfg);
+
+#endif /* SOC_INTEL_COMMON_BLOCK_GSPI_H */