diff options
Diffstat (limited to 'src/soc/intel/common/block/cpu/cpulib.c')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index dac654fea6..0ac8dda1a4 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -8,6 +8,7 @@ #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> +#include <soc/soc_chip.h> #include <stdint.h> /* @@ -254,6 +255,26 @@ uint32_t cpu_get_max_ratio(void) return ratio_max; } +void configure_tcc_thermal_target(void) +{ + const config_t *conf = config_of_soc(); + msr_t msr; + + /* Set TCC activation offset */ + msr = rdmsr(MSR_PLATFORM_INFO); + if ((msr.lo & BIT(30)) && conf->tcc_offset) { + msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); + msr.lo |= (conf->tcc_offset & 0xf) << 24; + wrmsr(MSR_TEMPERATURE_TARGET, msr); + } + msr = rdmsr(MSR_TEMPERATURE_TARGET); + /* Time Window Tau Bits [6:0] */ + msr.lo &= ~0x7f; + msr.lo |= 0xe6; /* setting 100ms thermal time window */ + wrmsr(MSR_TEMPERATURE_TARGET, msr); +} + uint32_t cpu_get_bus_clock(void) { /* CPU bus clock is set by default here to 100MHz. |