diff options
Diffstat (limited to 'src/soc/intel/common/basecode/tom/Kconfig')
| -rw-r--r-- | src/soc/intel/common/basecode/tom/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/common/basecode/tom/Kconfig b/src/soc/intel/common/basecode/tom/Kconfig new file mode 100644 index 0000000000..ff91725a52 --- /dev/null +++ b/src/soc/intel/common/basecode/tom/Kconfig @@ -0,0 +1,15 @@ +config SOC_INTEL_COMMON_BASECODE_TOM + bool + default n + help + Driver code to store the top_of_ram (TOM) address into + non-volatile space (CMOS) during the first boot and use + it across all consecutive boot. + + Purpose of this driver code is to cache the TOM (with a + fixed size) for all consecutive boots even before calling + into the FSP. Otherwise, this range remains un-cached until postcar + boot stage updates the MTRR programming. FSP-M and late romstage + uses this uncached TOM range for various purposes and having the + ability to cache this range beforehand would help to optimize the boot + time (more than 50ms). |