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-rw-r--r--src/soc/intel/cannonlake/acpi.c2
-rw-r--r--src/soc/intel/cannonlake/include/soc/cpu.h1
-rw-r--r--src/soc/intel/cannonlake/include/soc/romstage.h1
3 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 4fd92415af..84dfdad286 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -17,12 +17,10 @@
#include <arch/acpi.h>
#include <arch/acpigen.h>
-#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
#include <chip.h>
-#include <cpu/cpu.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/cpulib.h>
#include <intelblocks/pmclib.h>
diff --git a/src/soc/intel/cannonlake/include/soc/cpu.h b/src/soc/intel/cannonlake/include/soc/cpu.h
index 1e3e2b4cb1..0e027d3456 100644
--- a/src/soc/intel/cannonlake/include/soc/cpu.h
+++ b/src/soc/intel/cannonlake/include/soc/cpu.h
@@ -17,7 +17,6 @@
#ifndef _SOC_CANNONLAKE_CPU_H_
#define _SOC_CANNONLAKE_CPU_H_
-#include <arch/cpu.h>
#include <device/device.h>
#include <intelblocks/msr.h>
diff --git a/src/soc/intel/cannonlake/include/soc/romstage.h b/src/soc/intel/cannonlake/include/soc/romstage.h
index 9ea60ae93e..a58ace59a5 100644
--- a/src/soc/intel/cannonlake/include/soc/romstage.h
+++ b/src/soc/intel/cannonlake/include/soc/romstage.h
@@ -17,7 +17,6 @@
#ifndef _SOC_ROMSTAGE_H_
#define _SOC_ROMSTAGE_H_
-#include <arch/cpu.h>
#include <fsp/api.h>
void mainboard_memory_init_params(FSPM_UPD *mupd);