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-rw-r--r--src/soc/intel/cannonlake/acpi/gpio.asl8
-rw-r--r--src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl8
-rw-r--r--src/soc/intel/cannonlake/gpio.c22
-rw-r--r--src/soc/intel/cannonlake/gpio_cnp_h.c22
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h100
-rw-r--r--src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h100
6 files changed, 130 insertions, 130 deletions
diff --git a/src/soc/intel/cannonlake/acpi/gpio.asl b/src/soc/intel/cannonlake/acpi/gpio.asl
index e3e1e8cb6c..71524decba 100644
--- a/src/soc/intel/cannonlake/acpi/gpio.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio.asl
@@ -61,7 +61,7 @@ Device (GPIO)
Method (GADD, 1, NotSerialized)
{
/* GPIO Community 0 */
- If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPIO_RSVD_11)))
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, SPI0_CLK_LOOPBK)))
{
Store (PID_GPIOCOM0, Local0)
Subtract (Arg0, GPP_A0, Local1)
@@ -79,13 +79,13 @@ Method (GADD, 1, NotSerialized)
Subtract (Arg0, GPD0, Local1)
}
/* GPIO Community 3 */
- If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, GPIO_RSVD_38)))
+ If (LAnd (LGreaterEqual (Arg0, HDA_BCLK), LLessEqual (Arg0, TRIGGER_OUT)))
{
Store (PID_GPIOCOM3, Local0)
Subtract (Arg0, HDA_BCLK, Local1)
}
- /* GPIO Community 04*/
- If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPIO_RSVD_27)))
+ /* GPIO Community 4*/
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, CL_RST_B)))
{
Store (PID_GPIOCOM4, Local0)
Subtract (Arg0, GPP_C0, Local1)
diff --git a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
index 114b7b7169..da0756f62a 100644
--- a/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
+++ b/src/soc/intel/cannonlake/acpi/gpio_cnp_h.asl
@@ -67,25 +67,25 @@ Device (GPIO)
Method (GADD, 1, NotSerialized)
{
/* GPIO Community 0 */
- If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GPP_B23)))
+ If (LAnd (LGreaterEqual (Arg0, GPP_A0), LLessEqual (Arg0, GSPI1_CLK_LOOPBK)))
{
Store (PID_GPIOCOM0, Local0)
Subtract (Arg0, GPP_A0, Local1)
}
/* GPIO Community 1 */
- If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, GPP_G7)))
+ If (LAnd (LGreaterEqual (Arg0, GPP_C0), LLessEqual (Arg0, vSSP2_RXD)))
{
Store (PID_GPIOCOM1, Local0)
Subtract (Arg0, GPP_C0, Local1)
}
/* GPIO Community 3*/
- If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, GPP_F23)))
+ If (LAnd (LGreaterEqual (Arg0, GPP_K0), LLessEqual (Arg0, SPI0_CLK_LOOPBK)))
{
Store (PID_GPIOCOM3, Local0)
Subtract (Arg0, GPP_K0, Local1)
}
/* GPIO Community 4*/
- If (LAnd (LGreaterEqual (Arg0, GPP_I0), LLessEqual (Arg0, GPP_J11)))
+ If (LAnd (LGreaterEqual (Arg0, HDACPU_SDI), LLessEqual (Arg0, GPP_J11)))
{
Store (PID_GPIOCOM4, Local0)
Subtract (Arg0, GPP_I0, Local1)
diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index 91ac47c0b5..8e08a4b80b 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -32,14 +32,14 @@ static const struct reset_mapping rst_map_com0[] = {
* linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
*/
static const struct pad_group cnl_community0_groups[] = {
- INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */
- INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */
+ INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */
+ INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */
INTEL_GPP_BASE(GPP_A0, GPP_G0, GPP_G7, 64), /* GPP_G */
- INTEL_GPP(GPP_A0, GPIO_RSVD_3, GPIO_RSVD_11), /* SPI */
+ INTEL_GPP(GPP_A0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */
};
static const struct pad_group cnl_community1_groups[] = {
- INTEL_GPP_BASE(GPP_D0, GPP_D0, GPIO_RSVD_12, 96), /* GPP_D */
+ INTEL_GPP_BASE(GPP_D0, GPP_D0, GSPI2_CLK_LOOPBK, 96), /* GPP_D */
INTEL_GPP_BASE(GPP_D0, GPP_F0, GPP_F23, 128), /* GPP_F */
INTEL_GPP_BASE(GPP_D0, GPP_H0, GPP_H23, 160), /* GPP_H */
INTEL_GPP_BASE(GPP_D0, CNV_BTEN, vSD3_CD_B, 192), /* VGPIO */
@@ -52,15 +52,15 @@ static const struct pad_group cnl_community2_groups[] = {
/* This community is not visible to the OS */
static const struct pad_group cnl_community3_groups[] = {
- INTEL_GPP(HDA_BCLK, HDA_BCLK, SSP1_TXD), /* AZA */
- INTEL_GPP(HDA_BCLK, GPIO_RSVD_28, GPIO_RSVD_38), /* CPU */
+ INTEL_GPP(HDA_BCLK, HDA_BCLK, I2S1_TXD), /* AZA */
+ INTEL_GPP(HDA_BCLK, HDACPU_SDI, TRIGGER_OUT), /* CPU */
};
static const struct pad_group cnl_community4_groups[] = {
INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 256), /* GPP_C */
INTEL_GPP_BASE(GPP_C0, GPP_E0, GPP_E23, 288), /* GPP_E */
- INTEL_GPP(GPP_C0, GPIO_RSVD_13, GPIO_RSVD_21), /* JTAG */
- INTEL_GPP(GPP_C0, GPIO_RSVD_22, GPIO_RSVD_27), /* HVMOS */
+ INTEL_GPP(GPP_C0, PCH_TDO, ITP_PMODE), /* JTAG */
+ INTEL_GPP(GPP_C0, EDP_BKLTEN, CL_RST_B), /* HVMOS */
};
static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
@@ -68,7 +68,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
[COMM_0] = {
.port = PID_GPIOCOM0,
.first_pad = GPP_A0,
- .last_pad = GPIO_RSVD_11,
+ .last_pad = SPI0_CLK_LOOPBK,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -128,7 +128,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
[COMM_3] = {
.port = PID_GPIOCOM3,
.first_pad = HDA_BCLK,
- .last_pad = GPIO_RSVD_38,
+ .last_pad = TRIGGER_OUT,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -148,7 +148,7 @@ static const struct pad_community cnl_communities[TOTAL_GPIO_COMM] = {
[COMM_4] = {
.port = PID_GPIOCOM4,
.first_pad = GPP_C0,
- .last_pad = GPIO_RSVD_27,
+ .last_pad = CL_RST_B,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
diff --git a/src/soc/intel/cannonlake/gpio_cnp_h.c b/src/soc/intel/cannonlake/gpio_cnp_h.c
index eb333fd00a..a7b1781e82 100644
--- a/src/soc/intel/cannonlake/gpio_cnp_h.c
+++ b/src/soc/intel/cannonlake/gpio_cnp_h.c
@@ -32,15 +32,15 @@ static const struct reset_mapping rst_map_com0[] = {
* linux/drivers/pinctrl/intel/pinctrl-cannonlake.c
*/
static const struct pad_group cnl_community0_groups[] = {
- INTEL_GPP_BASE(GPP_A0, GPP_A0, GPIO_RSVD_0, 0), /* GPP_A */
- INTEL_GPP_BASE(GPP_A0, GPP_B0, GPIO_RSVD_2, 32), /* GPP_B */
+ INTEL_GPP_BASE(GPP_A0, GPP_A0, ESPI_CLK_LOOPBK, 0), /* GPP_A */
+ INTEL_GPP_BASE(GPP_A0, GPP_B0, GSPI1_CLK_LOOPBK, 32), /* GPP_B */
};
static const struct pad_group cnl_community1_groups[] = {
INTEL_GPP_BASE(GPP_C0, GPP_C0, GPP_C23, 64), /* GPP_C */
INTEL_GPP_BASE(GPP_C0, GPP_D0, GPP_D23, 96), /* GPP_D */
INTEL_GPP_BASE(GPP_C0, GPP_G0, GPP_G7, 128), /* GPP_G */
- INTEL_GPP(GPP_C0, GPIO_RSVD_3, GPIO_RSVD_10), /* AZA */
+ INTEL_GPP(GPP_C0, HDA_BCLK, I2S1_TXD), /* AZA */
INTEL_GPP_BASE(GPP_C0, CNV_BTEN, vISH_UART1_RTS_B, 160),/* VGPIO_0 */
INTEL_GPP(GPP_C0, vCNV_BT_I2S_BCLK, vSSP2_RXD), /* VGPIO_1 */
};
@@ -55,14 +55,14 @@ static const struct pad_group cnl_community3_groups[] = {
INTEL_GPP_BASE(GPP_K0, GPP_H0, GPP_H23, 224), /* GPP_H */
INTEL_GPP_BASE(GPP_K0, GPP_E0, GPP_E12, 256), /* GPP_E */
INTEL_GPP_BASE(GPP_K0, GPP_F0, GPP_F23, 288), /* GPP_F */
- INTEL_GPP(GPP_K0, GPIO_RSVD_11, GPIO_RSVD_19), /* SPI */
+ INTEL_GPP(GPP_K0, SPI0_IO_2, SPI0_CLK_LOOPBK), /* SPI */
};
static const struct pad_group cnl_community4_groups[] = {
- INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_20, GPIO_RSVD_30), /* CPU */
- INTEL_GPP(GPIO_RSVD_20, GPIO_RSVD_31, GPIO_RSVD_39), /* JTAG */
- INTEL_GPP_BASE(GPIO_RSVD_20, GPP_I0, GPP_I14, 320), /* GPP_I */
- INTEL_GPP_BASE(GPIO_RSVD_20, GPP_J0, GPP_J11, 352), /* GPP_J */
+ INTEL_GPP(HDACPU_SDI, HDACPU_SDI, TRIGGER_OUT), /* CPU */
+ INTEL_GPP(HDACPU_SDI, PCH_TDO, ITP_PMODE), /* JTAG */
+ INTEL_GPP_BASE(HDACPU_SDI, GPP_I0, GPP_I14, 320), /* GPP_I */
+ INTEL_GPP_BASE(HDACPU_SDI, GPP_J0, GPP_J11, 352), /* GPP_J */
};
static const struct pad_community cnl_communities[] = {
@@ -70,7 +70,7 @@ static const struct pad_community cnl_communities[] = {
[COMM_0] = {
.port = PID_GPIOCOM0,
.first_pad = GPP_A0,
- .last_pad = GPIO_RSVD_2,
+ .last_pad = GSPI1_CLK_LOOPBK,
.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -130,7 +130,7 @@ static const struct pad_community cnl_communities[] = {
[COMM_3] = {
.port = PID_GPIOCOM3,
.first_pad = GPP_K0,
- .last_pad = GPIO_RSVD_19,
+ .last_pad = SPI0_CLK_LOOPBK,
.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
.host_own_reg_0 = HOSTSW_OWN_REG_0,
@@ -149,7 +149,7 @@ static const struct pad_community cnl_communities[] = {
/* GPP I, J */
[COMM_4] = {
.port = PID_GPIOCOM4,
- .first_pad = GPIO_RSVD_20,
+ .first_pad = HDACPU_SDI,
.last_pad = GPP_J11,
.num_gpi_regs = NUM_GPIO_COM4_GPI_REGS,
.pad_cfg_base = PAD_CFG_BASE,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
index f5a926296e..b5d34dcb5f 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h
@@ -57,7 +57,7 @@
#define GPP_A21 21
#define GPP_A22 22
#define GPP_A23 23
-#define GPIO_RSVD_0 24
+#define ESPI_CLK_LOOPBK 24
/* Group B */
#define GPP_B0 25
#define GPP_B1 26
@@ -83,8 +83,8 @@
#define GPP_B21 46
#define GPP_B22 47
#define GPP_B23 48
-#define GPIO_RSVD_1 49
-#define GPIO_RSVD_2 50
+#define GSPI0_CLK_LOOPBK 49
+#define GSPI1_CLK_LOOPBK 50
/* Group G */
#define GPP_G0 51
#define GPP_G1 52
@@ -95,17 +95,17 @@
#define GPP_G6 57
#define GPP_G7 58
/* Group SPI */
-#define GPIO_RSVD_3 59
-#define GPIO_RSVD_4 60
-#define GPIO_RSVD_5 61
-#define GPIO_RSVD_6 62
-#define GPIO_RSVD_7 63
-#define GPIO_RSVD_8 64
-#define GPIO_RSVD_9 65
-#define GPIO_RSVD_10 66
-#define GPIO_RSVD_11 67
+#define SPI0_IO_2 59
+#define SPI0_IO_3 60
+#define SPI0_MOSI 61
+#define SPI0_MISO 62
+#define SPI0_CS2_B 63
+#define SPI0_CS0_B 64
+#define SPI0_CS1_B 65
+#define SPI0_CLK 66
+#define SPI0_CLK_LOOPBK 67
-#define NUM_GPIO_COM0_PADS (GPIO_RSVD_11 - GPP_A0 + 1)
+#define NUM_GPIO_COM0_PADS (SPI0_CLK_LOOPBK - GPP_A0 + 1)
/* Group D */
#define GPP_D0 68
@@ -132,7 +132,7 @@
#define GPP_D21 89
#define GPP_D22 90
#define GPP_D23 91
-#define GPIO_RSVD_12 92
+#define GSPI2_CLK_LOOPBK 92
/* Group F */
#define GPP_F0 93
#define GPP_F1 94
@@ -188,7 +188,7 @@
#define CNV_GNEN 142
#define CNV_WFEN 143
#define CNV_WCEN 144
-#define CNV_BT_HOST_WAKEB 145
+#define CNV_BT_HOST_WAKE_B 145
#define CNV_BT_IF_SELECT 146
#define vCNV_BT_UART_TXD 147
#define vCNV_BT_UART_RXD 148
@@ -222,7 +222,7 @@
#define vSSP2_SFRM 176
#define vSSP2_TXD 177
#define vSSP2_RXD 178
-#define vCNV_GNSS_HOST_WAKEB 179
+#define vCNV_GNSS_HOST_WAKE_B 179
#define vSD3_CD_B 180
#define NUM_GPIO_COM1_PADS (vSD3_CD_B - GPP_D0 + 1)
@@ -278,26 +278,26 @@
#define GPP_E22 227
#define GPP_E23 228
/* Group Jtag */
-#define GPIO_RSVD_13 229
-#define GPIO_RSVD_14 230
-#define GPIO_RSVD_15 231
-#define GPIO_RSVD_16 232
-#define GPIO_RSVD_17 233
-#define GPIO_RSVD_18 234
-#define GPIO_RSVD_19 235
-#define GPIO_RSVD_20 236
-#define GPIO_RSVD_21 237
+#define PCH_TDO 229
+#define PCH_JTAGX 230
+#define PROC_PRDY_B 231
+#define PROC_PREQ_B 232
+#define CPU_TRST_B 233
+#define PCH_TDI 234
+#define PCH_TMS 235
+#define PCH_TCK 236
+#define ITP_PMODE 237
/* Group HVMOS */
-#define GPIO_RSVD_22 238
-#define GPIO_RSVD_23 239
-#define GPIO_RSVD_24 240
-#define GPIO_RSVD_25 241
-#define GPIO_RSVD_26 242
-#define GPIO_RSVD_27 243
+#define EDP_BKLTEN 238
+#define EDP_BKLTCTL 239
+#define EDP_VDDEN 240
+#define SYS_PWROK 241
+#define SYS_RESET_B 242
+#define CL_RST_B 243
-#define NUM_GPIO_COM4_PADS (GPIO_RSVD_27 - GPP_C0 + 1)
+#define NUM_GPIO_COM4_PADS (CL_RST_B - GPP_C0 + 1)
-/* Group GPD */
+/* Group GPD */
#define GPD0 244
#define GPD1 245
#define GPD2 246
@@ -316,27 +316,27 @@
/* Group AZA */
#define HDA_BCLK 256
-#define HDA_RSTB 257
+#define HDA_RST_B 257
#define HDA_SYNC 258
#define HDA_SDO 259
-#define HDA_SDI_0 260
-#define HDA_SDI_1 261
-#define SSP1_SFRM 262
-#define SSP1_TXD 263
+#define HDA_SDI0 260
+#define HDA_SDI1 261
+#define I2S1_SFRM 262
+#define I2S1_TXD 263
/* Group CPU */
-#define GPIO_RSVD_28 264
-#define GPIO_RSVD_29 265
-#define GPIO_RSVD_30 266
-#define GPIO_RSVD_31 267
-#define GPIO_RSVD_32 268
-#define GPIO_RSVD_33 269
-#define GPIO_RSVD_34 270
-#define GPIO_RSVD_35 271
-#define GPIO_RSVD_36 272
-#define GPIO_RSVD_37 273
-#define GPIO_RSVD_38 274
+#define HDACPU_SDI 264
+#define HDACPU_SDO 265
+#define HDACPU_SCLK 266
+#define PM_SYNC 267
+#define PECI_IO 268
+#define CPUPWRGD 269
+#define THRMTRIP_B 270
+#define PLTRST_CPU_B 271
+#define PM_DOWN 272
+#define TRIGGER_IN 273
+#define TRIGGER_OUT 274
-#define NUM_GPIO_COM3_PADS (GPIO_RSVD_38 - HDA_BCLK + 1)
+#define NUM_GPIO_COM3_PADS (TRIGGER_OUT - HDA_BCLK + 1)
#define TOTAL_PADS 275
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
index dde0a65a2a..dc332d1fe4 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
@@ -53,7 +53,7 @@
#define GPP_A21 21
#define GPP_A22 22
#define GPP_A23 23
-#define GPIO_RSVD_0 24
+#define ESPI_CLK_LOOPBK 24
/* Group B */
#define GPP_B0 25
@@ -80,10 +80,10 @@
#define GPP_B21 46
#define GPP_B22 47
#define GPP_B23 48
-#define GPIO_RSVD_1 49
-#define GPIO_RSVD_2 50
+#define GSPI0_CLK_LOOPBK 49
+#define GSPI1_CLK_LOOPBK 50
-#define NUM_GPIO_COM0_PADS (GPIO_RSVD_2 - GPP_A0 + 1)
+#define NUM_GPIO_COM0_PADS (GSPI1_CLK_LOOPBK - GPP_A0 + 1)
/* Group C */
#define GPP_C0 51
@@ -148,22 +148,22 @@
#define GPP_G7 106
/* AZA */
-#define GPIO_RSVD_3 107
-#define GPIO_RSVD_4 108
-#define GPIO_RSVD_5 109
-#define GPIO_RSVD_6 110
-#define GPIO_RSVD_7 111
-#define GPIO_RSVD_8 112
-#define GPIO_RSVD_9 113
-#define GPIO_RSVD_10 114
+#define HDA_BCLK 107
+#define HDA_RST_B 108
+#define HDA_SYNC 109
+#define HDA_SDO 110
+#define HDA_SDI0 111
+#define HDA_SDI1 112
+#define I2S1_SFRM 113
+#define I2S1_TXD 114
/* VGPIO_0 */
#define CNV_BTEN 115
#define CNV_GNEN 116
#define CNV_WFEN 117
#define CNV_WCEN 118
-#define CNV_BT_HOST_WAKEB 119
-#define vCNV_GNSS_HOST_WAKEB 120
+#define CNV_BT_HOST_WAKE_B 119
+#define vCNV_GNSS_HOST_WAKE_B 120
#define vSD3_CD_B 121
#define CNV_BT_IF_SELECT 122
#define vCNV_BT_UART_TXD 123
@@ -181,11 +181,11 @@
#define vUART0_TXD 135
#define vUART0_RXD 136
#define vUART0_CTS_B 137
-#define vUART0_RTSB 138
+#define vUART0_RTS_B 138
#define vISH_UART0_TXD 139
#define vISH_UART0_RXD 140
#define vISH_UART0_CTS_B 141
-#define vISH_UART0_RTSB 142
+#define vISH_UART0_RTS_B 142
#define vISH_UART1_TXD 143
#define vISH_UART1_RXD 144
#define vISH_UART1_CTS_B 145
@@ -296,41 +296,41 @@
#define GPP_F23 239
/* SPI */
-#define GPIO_RSVD_11 240
-#define GPIO_RSVD_12 241
-#define GPIO_RSVD_13 242
-#define GPIO_RSVD_14 243
-#define GPIO_RSVD_15 244
-#define GPIO_RSVD_16 245
-#define GPIO_RSVD_17 246
-#define GPIO_RSVD_18 247
-#define GPIO_RSVD_19 248
+#define SPI0_IO_2 240
+#define SPI0_IO_3 241
+#define SPI0_MOSI 242
+#define SPI0_MISO 243
+#define SPI0_CS2_B 244
+#define SPI0_CS0_B 245
+#define SPI0_CS1_B 246
+#define SPI0_CLK 247
+#define SPI0_CLK_LOOPBK 248
-#define NUM_GPIO_COM3_PADS (GPIO_RSVD_19 - GPP_K0 + 1)
+#define NUM_GPIO_COM3_PADS (SPI0_CLK_LOOPBK - GPP_K0 + 1)
/* CPU */
-#define GPIO_RSVD_20 249
-#define GPIO_RSVD_21 250
-#define GPIO_RSVD_22 251
-#define GPIO_RSVD_23 252
-#define GPIO_RSVD_24 253
-#define GPIO_RSVD_25 254
-#define GPIO_RSVD_26 255
-#define GPIO_RSVD_27 256
-#define GPIO_RSVD_28 257
-#define GPIO_RSVD_29 258
-#define GPIO_RSVD_30 259
+#define HDACPU_SDI 249
+#define HDACPU_SDO 250
+#define HDACPU_SCLK 251
+#define PM_SYNC 252
+#define PECI_IO 253
+#define CPUPWRGD 254
+#define THRMTRIP_B 255
+#define PLTRST_CPU_B 256
+#define PM_DOWN 257
+#define TRIGGER_IN 258
+#define TRIGGER_OUT 259
/* JTAG */
-#define GPIO_RSVD_31 260
-#define GPIO_RSVD_32 261
-#define GPIO_RSVD_33 262
-#define GPIO_RSVD_34 263
-#define GPIO_RSVD_35 264
-#define GPIO_RSVD_36 265
-#define GPIO_RSVD_37 266
-#define GPIO_RSVD_38 267
-#define GPIO_RSVD_39 268
+#define PCH_TDO 260
+#define PCH_JTAGX 261
+#define PROC_PRDY_B 262
+#define PROC_PREQ_B 263
+#define CPU_TRST_B 264
+#define PCH_TDI 265
+#define PCH_TMS 266
+#define PCH_TCK 267
+#define ITP_PMODE 268
/* Group I */
#define GPP_I0 269
@@ -348,9 +348,9 @@
#define GPP_I12 281
#define GPP_I13 282
#define GPP_I14 283
-#define GPIO_RSVD_40 284
-#define GPIO_RSVD_41 285
-#define GPIO_RSVD_42 286
+#define SYS_PWROK 284
+#define SYS_RESET_B 285
+#define CL_RST_B 286
/* Group J */
#define GPP_J0 287
@@ -368,7 +368,7 @@
#define NUM_GPIO_COM4_PADS (GPP_J11 - GPP_I0 + 1)
-/* Group GPD */
+/* Group GPD */
#define GPD0 299
#define GPD1 300
#define GPD2 301
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 02:57:28 +0000