diff options
Diffstat (limited to 'src/soc/intel/cannonlake/romstage')
-rw-r--r-- | src/soc/intel/cannonlake/romstage/power_state.c | 88 | ||||
-rw-r--r-- | src/soc/intel/cannonlake/romstage/romstage.c | 9 |
2 files changed, 90 insertions, 7 deletions
diff --git a/src/soc/intel/cannonlake/romstage/power_state.c b/src/soc/intel/cannonlake/romstage/power_state.c index 2c45ad9354..46048db75b 100644 --- a/src/soc/intel/cannonlake/romstage/power_state.c +++ b/src/soc/intel/cannonlake/romstage/power_state.c @@ -18,14 +18,94 @@ #include <arch/io.h> #include <cbmem.h> #include <console/console.h> +#include <device/device.h> +#include <intelblocks/pmclib.h> +#include <string.h> +#include <soc/pci_devs.h> #include <soc/pm.h> static struct chipset_power_state power_state CAR_GLOBAL; -/* Fill power state structure from ACPI PM registers */ -struct chipset_power_state *fill_power_state(void) +static void migrate_power_state(int is_recovery) { - struct chipset_power_state *ps = car_get_var_ptr(&power_state); + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; - return ps; + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) + +static inline int deep_s3_enabled(void) +{ + uint32_t deep_s3_pol; + + deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); + return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); +} + +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +int soc_prev_sleep_state(const struct chipset_power_state *ps, + int prev_sleep_state) +{ + + /* + * Check for any power failure to determine if this a wake from + * S5 because the PCH does not set the WAK_STS bit when waking + * from a true G3 state. + */ + if (ps->gen_pmcon_b & (PWR_FLR | SUS_PWR_FLR)) + prev_sleep_state = ACPI_S5; + + /* + * If waking from S3 determine if deep S3 is enabled. If not, + * need to check both deep sleep well and normal suspend well. + * Otherwise just check deep sleep well. + */ + if (prev_sleep_state == ACPI_S3) { + /* PWR_FLR represents deep sleep power well loss. */ + uint32_t mask = PWR_FLR; + + /* If deep s3 isn't enabled check the suspend well too. */ + if (!deep_s3_enabled()) + mask |= SUS_PWR_FLR; + + if (ps->gen_pmcon_b & mask) + prev_sleep_state = ACPI_S5; + } + + return prev_sleep_state; +} + +void soc_fill_power_state(struct chipset_power_state *ps) +{ + uint16_t tcobase; + uint8_t *pmc; + + tcobase = smbus_tco_regs(); + + ps->tco1_sts = inw(tcobase + TCO1_STS); + ps->tco2_sts = inw(tcobase + TCO2_STS); + + printk(BIOS_DEBUG, "TCO_STS: %04x %04x\n", + ps->tco1_sts, ps->tco2_sts); + + pmc = pmc_mmio_regs(); + ps->gen_pmcon_a = read32(pmc + GEN_PMCON_A); + ps->gen_pmcon_b = read32(pmc + GEN_PMCON_B); + ps->gblrst_cause[0] = read32(pmc + GBLRST_CAUSE0); + ps->gblrst_cause[1] = read32(pmc + GBLRST_CAUSE1); + + printk(BIOS_DEBUG, "GEN_PMCON: %08x %08x\n", + ps->gen_pmcon_a, ps->gen_pmcon_b); + + printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", + ps->gblrst_cause[0], ps->gblrst_cause[1]); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 2f8617e4cf..ab0e19bdc6 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,30 +14,33 @@ */ #include <arch/io.h> +#include <arch/early_variables.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> #include <fsp/util.h> +#include <intelblocks/pmclib.h> #include <memory_info.h> #include <soc/pm.h> #include <soc/romstage.h> #include <timestamp.h> +static struct chipset_power_state power_state CAR_GLOBAL; + asmlinkage void car_stage_entry(void) { bool s3wake; struct postcar_frame pcf; uintptr_t top_of_ram; - struct chipset_power_state *ps; + struct chipset_power_state *ps = car_get_var_ptr(&power_state); console_init(); /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); - ps = fill_power_state(); timestamp_add_now(TS_START_ROMSTAGE); - s3wake = ps->prev_sleep_state == ACPI_S3; + s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1 * KiB)) die("Unable to initialize postcar frame.\n"); |