aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/cannonlake/fsp_params.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/cannonlake/fsp_params.c')
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 8788838c3f..a3b5588b77 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -319,10 +319,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(config->PcieClkSrcUsage));
memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq,
sizeof(config->PcieClkSrcClkReq));
+
+ memcpy(params->PcieRpAdvancedErrorReporting,
+ config->PcieRpAdvancedErrorReporting,
+ sizeof(params->PcieRpAdvancedErrorReporting));
+
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
- sizeof(config->PcieRpHotPlug));
+ sizeof(params->PcieRpHotPlug));
+
+ for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
+ params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
+ if (config->PcieRpAspm[i])
+ params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
+ };
+
/* eMMC and SD */
dev = pcidev_path_on_root(PCH_DEVFN_EMMC);