diff options
Diffstat (limited to 'src/soc/intel/broadwell/romstage')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/raminit.c | 196 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/report_platform.c | 182 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 67 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/systemagent.c | 58 |
5 files changed, 0 insertions, 507 deletions
diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc deleted file mode 100644 index 65cb9adee5..0000000000 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -romstage-y += raminit.c -romstage-y += report_platform.c -romstage-y += romstage.c -romstage-y += systemagent.c diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c deleted file mode 100644 index 7020ddfe0d..0000000000 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <assert.h> -#include <cbfs.h> -#include <cbmem.h> -#include <cf9_reset.h> -#include <console/console.h> -#include <device/pci_def.h> -#include <memory_info.h> -#include <mrc_cache.h> -#include <string.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#endif -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/iomap.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> - -static const char *const ecc_decoder[] = { - "inactive", - "active on IO", - "disabled on IO", - "active", -}; - -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ -static void report_memory_config(void) -{ - int i; - - const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); - - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); - - printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - (addr_decoder_common >> 0) & 3, - (addr_decoder_common >> 2) & 3, - (addr_decoder_common >> 4) & 3); - - for (i = 0; i < NUM_CHANNELS; i++) { - const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); - - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); - printk(BIOS_DEBUG, " enhanced interleave mode %s\n", - ((ch_conf >> 22) & 1) ? "on" : "off"); - - printk(BIOS_DEBUG, " rank interleave %s\n", - ((ch_conf >> 21) & 1) ? "on" : "off"); - - printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", - ((ch_conf >> 0) & 0xff) * 256, - ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 17) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? "" : ", selected"); - - printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", - ((ch_conf >> 8) & 0xff) * 256, - ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", - ((ch_conf >> 18) & 1) ? "dual" : "single", - ((ch_conf >> 16) & 1) ? ", selected" : ""); - } -} - -/* - * Find PEI executable in coreboot filesystem and execute it. - */ -void raminit(struct pei_data *pei_data) -{ - size_t mrc_size; - struct memory_info *mem_info; - pei_wrapper_entry_t entry; - int ret; - struct cbfsf f; - uint32_t type = CBFS_TYPE_MRC; - - broadwell_fill_pei_data(pei_data); - - if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && - vboot_recovery_mode_enabled()) { - /* Recovery mode does not use MRC cache */ - printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else { - /* Assume boot device is memory mapped. */ - assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); - - pei_data->saved_data = - mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, - &mrc_size); - if (pei_data->saved_data) { - /* MRC cache found */ - pei_data->saved_data_size = mrc_size; - } else if (pei_data->boot_mode == ACPI_S3) { - /* Waking from S3 and no cache. */ - printk(BIOS_DEBUG, - "No MRC cache found in S3 resume path.\n"); - post_code(POST_RESUME_FAILURE); - system_reset(); - } else { - printk(BIOS_DEBUG, "No MRC cache found.\n"); - } - } - - /* - * Do not use saved pei data. Can be set by mainboard romstage - * to force a full train of memory on every boot. - */ - if (pei_data->disable_saved_data) { - printk(BIOS_DEBUG, "Disabling PEI saved data by request\n"); - pei_data->saved_data = NULL; - pei_data->saved_data_size = 0; - } - - /* Determine if mrc.bin is in the cbfs. */ - if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) - die("mrc.bin not found!"); - /* We don't care about leaking the mapping */ - entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); - if (entry == NULL) { - printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); - return; - } - - printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); - - ret = entry(pei_data); - if (ret < 0) - die("pei_data version mismatch\n"); - - /* Print the MRC version after executing the UEFI PEI stage. */ - u32 version = MCHBAR32(MRC_REVISION); - printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", - (version >> 24) & 0xff, (version >> 16) & 0xff, - (version >> 8) & 0xff, (version >> 0) & 0xff); - - report_memory_config(); - - if (pei_data->boot_mode != ACPI_S3) { - cbmem_initialize_empty(); - } else if (cbmem_initialize()) { - printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); - /* Failed S3 resume, reset to come up cleanly */ - system_reset(); - } - - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, - pei_data->data_to_save_size); - - if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) - mrc_cache_stash_data(MRC_TRAINING_DATA, 0, - pei_data->data_to_save, - pei_data->data_to_save_size); - - printk(BIOS_DEBUG, "create cbmem for dimm information\n"); - mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); - - if (!mem_info) { - printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n"); - return; - } - - memset(mem_info, 0, sizeof(*mem_info)); - /* Translate pei_memory_info struct data into memory_info struct */ - mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; - for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) { - struct dimm_info *dimm = &mem_info->dimm[i]; - const struct pei_dimm_info *pei_dimm = - &pei_data->meminfo.dimm[i]; - dimm->dimm_size = pei_dimm->dimm_size; - dimm->ddr_type = pei_dimm->ddr_type; - dimm->ddr_frequency = pei_dimm->ddr_frequency; - dimm->rank_per_dimm = pei_dimm->rank_per_dimm; - dimm->channel_num = pei_dimm->channel_num; - dimm->dimm_num = pei_dimm->dimm_num; - dimm->bank_locator = pei_dimm->bank_locator; - memcpy(&dimm->serial, &pei_dimm->serial, - MIN(sizeof(dimm->serial), sizeof(pei_dimm->serial))); - memcpy(&dimm->module_part_number, - &pei_dimm->module_part_number, - MIN(sizeof(dimm->module_part_number), - sizeof(pei_dimm->module_part_number))); - dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; - dimm->mod_id = pei_dimm->mod_id; - dimm->mod_type = pei_dimm->mod_type; - dimm->bus_width = pei_dimm->bus_width; - } -} diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c deleted file mode 100644 index 4ed84d7cea..0000000000 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ /dev/null @@ -1,182 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/cpu.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <device/pci.h> -#include <string.h> -#include <cpu/intel/microcode.h> -#include <cpu/x86/msr.h> -#include <soc/cpu.h> -#include <soc/pch.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> - -static struct { - u32 cpuid; - const char *name; -} cpu_table[] = { - { CPUID_HASWELL_A0, "Haswell A0" }, - { CPUID_HASWELL_B0, "Haswell B0" }, - { CPUID_HASWELL_C0, "Haswell C0" }, - { CPUID_HASWELL_ULT_B0, "Haswell ULT B0" }, - { CPUID_HASWELL_ULT, "Haswell ULT C0 or D0" }, - { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, - { CPUID_BROADWELL_C0, "Broadwell C0" }, - { CPUID_BROADWELL_D0, "Broadwell D0" }, - { CPUID_BROADWELL_E0, "Broadwell E0 or F0" }, -}; - -static struct { - u8 revid; - const char *name; -} mch_rev_table[] = { - { MCH_BROADWELL_REV_D0, "Broadwell D0" }, - { MCH_BROADWELL_REV_E0, "Broadwell E0" }, - { MCH_BROADWELL_REV_F0, "Broadwell F0" }, -}; - -static struct { - u16 lpcid; - const char *name; -} pch_table[] = { - { PCH_LPT_LP_SAMPLE, "LynxPoint LP Sample" }, - { PCH_LPT_LP_PREMIUM, "LynxPoint LP Premium" }, - { PCH_LPT_LP_MAINSTREAM, "LynxPoint LP Mainstream" }, - { PCH_LPT_LP_VALUE, "LynxPoint LP Value" }, - { PCH_WPT_HSW_U_SAMPLE, "Haswell U Sample" }, - { PCH_WPT_BDW_U_SAMPLE, "Broadwell U Sample" }, - { PCH_WPT_BDW_U_PREMIUM, "Broadwell U Premium" }, - { PCH_WPT_BDW_U_BASE, "Broadwell U Base" }, - { PCH_WPT_BDW_Y_SAMPLE, "Broadwell Y Sample" }, - { PCH_WPT_BDW_Y_PREMIUM, "Broadwell Y Premium" }, - { PCH_WPT_BDW_Y_BASE, "Broadwell Y Base" }, - { PCH_WPT_BDW_H, "Broadwell H" }, -}; - -static struct { - u16 igdid; - const char *name; -} igd_table[] = { - { IGD_HASWELL_ULT_GT1, "Haswell ULT GT1" }, - { IGD_HASWELL_ULT_GT2, "Haswell ULT GT2" }, - { IGD_HASWELL_ULT_GT3, "Haswell ULT GT3" }, - { IGD_BROADWELL_U_GT1, "Broadwell U GT1" }, - { IGD_BROADWELL_U_GT2, "Broadwell U GT2" }, - { IGD_BROADWELL_U_GT3_15W, "Broadwell U GT3 (15W)" }, - { IGD_BROADWELL_U_GT3_28W, "Broadwell U GT3 (28W)" }, - { IGD_BROADWELL_Y_GT2, "Broadwell Y GT2" }, - { IGD_BROADWELL_H_GT2, "Broadwell U GT2" }, - { IGD_BROADWELL_H_GT3, "Broadwell U GT3" }, -}; - -static void report_cpu_info(void) -{ - struct cpuid_result cpuidr; - u32 i, index, cpu_id, cpu_feature_flag; - char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */ - int vt, txt, aes; - const char *mode[] = {"NOT ", ""}; - const char *cpu_type = "Unknown"; - - index = 0x80000000; - cpuidr = cpuid(index); - if (cpuidr.eax < 0x80000004) { - strcpy(cpu_string, "Platform info not available"); - } else { - u32 *p = (u32 *)cpu_string; - for (i = 2; i <= 4 ; i++) { - cpuidr = cpuid(index + i); - *p++ = cpuidr.eax; - *p++ = cpuidr.ebx; - *p++ = cpuidr.ecx; - *p++ = cpuidr.edx; - } - } - /* Skip leading spaces in CPU name string */ - while (cpu_name[0] == ' ') - cpu_name++; - - cpu_id = cpu_get_cpuid(); - - /* Look for string to match the name */ - for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { - if (cpu_table[i].cpuid == cpu_id) { - cpu_type = cpu_table[i].name; - break; - } - } - - printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); - printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", - cpu_id, cpu_type, get_current_microcode_rev()); - - cpu_feature_flag = cpu_get_feature_flags_ecx(); - aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; - txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; - vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; - printk(BIOS_DEBUG, "CPU: AES %ssupported, TXT %ssupported, " - "VT %ssupported\n", mode[aes], mode[txt], mode[vt]); -} - -static void report_mch_info(void) -{ - int i; - u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); - const char *mch_type = "Unknown"; - - /* Look for string to match the revision for Broadwell U/Y */ - if (mch_device == MCH_BROADWELL_ID_U_Y) { - for (i = 0; i < ARRAY_SIZE(mch_rev_table); i++) { - if (mch_rev_table[i].revid == mch_revision) { - mch_type = mch_rev_table[i].name; - break; - } - } - } - - printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", - mch_device, mch_revision, mch_type); -} - -static void report_pch_info(void) -{ - int i; - u16 lpcid = pch_type(); - const char *pch_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { - pch_type = pch_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, pch_revision(), pch_type); -} - -static void report_igd_info(void) -{ - int i; - u16 igdid = pci_read_config16(SA_DEV_IGD, PCI_DEVICE_ID); - const char *igd_type = "Unknown"; - - for (i = 0; i < ARRAY_SIZE(igd_table); i++) { - if (igd_table[i].igdid == igdid) { - igd_type = igd_table[i].name; - break; - } - } - printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", - igdid, pci_read_config8(SA_DEV_IGD, PCI_REVISION_ID), igd_type); -} - -void report_platform_info(void) -{ - report_cpu_info(); - report_mch_info(); - report_pch_info(); - report_igd_info(); -} diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c deleted file mode 100644 index 2e5db76ce9..0000000000 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -#include <arch/romstage.h> -#include <console/console.h> -#include <elog.h> -#include <romstage_handoff.h> -#include <soc/gpio.h> -#include <soc/me.h> -#include <soc/pei_data.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <stdint.h> -#include <timestamp.h> - -/* Entry from cpu/intel/car/romstage.c. */ -void mainboard_romstage_entry(void) -{ - struct romstage_params rp = { 0 }; - - post_code(0x30); - - /* System Agent Early Initialization */ - systemagent_early_init(); - - /* PCH Early Initialization */ - pch_early_init(); - - /* Get power state */ - rp.power_state = fill_power_state(); - - elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); - - /* Print useful platform information */ - report_platform_info(); - - /* Set CPU frequency to maximum */ - set_max_freq(); - - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - - /* Fill in mainboard pei_date. */ - mainboard_pre_raminit(&rp); - - post_code(0x32); - - timestamp_add_now(TS_BEFORE_INITRAM); - - rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; - - /* Print ME state before MRC */ - intel_me_status(); - - /* Save ME HSIO version */ - intel_me_hsio_version(&rp.power_state->hsio_version, - &rp.power_state->hsio_checksum); - - /* Initialize RAM */ - raminit(&rp.pei_data); - - timestamp_add_now(TS_AFTER_INITRAM); - - romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); - - mainboard_post_raminit(&rp); -} diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c deleted file mode 100644 index 6bf7ba7a59..0000000000 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/mmio.h> -#include <device/pci_ops.h> -#include <device/pci_def.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/romstage.h> -#include <soc/systemagent.h> - -static void broadwell_setup_bars(void) -{ - /* Set up all hardcoded northbridge BARs */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); - - MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; - MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1; - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); - pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); -} - -void systemagent_early_init(void) -{ - const bool vtd_capable = - !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); - - broadwell_setup_bars(); - - /* Device enable: IGD and Mini-HD */ - pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); - - if (vtd_capable) { - /* setup BARs: zeroize top 32 bits; set enable bit */ - MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; - MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; - MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; - MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; - - /* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */ - u32 reg32; - reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); - write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), - reg32 | DMAR_LCKDN | PRSCAPDIS); - /* lock VTVC0BAR policy cfg registers */ - reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)); - write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), - reg32 | DMAR_LCKDN); - } -} |