aboutsummaryrefslogtreecommitdiff
path: root/src/soc/intel/broadwell/cpu.c
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel/broadwell/cpu.c')
-rw-r--r--src/soc/intel/broadwell/cpu.c18
1 files changed, 1 insertions, 17 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c
index 4bfa15d354..1312525814 100644
--- a/src/soc/intel/broadwell/cpu.c
+++ b/src/soc/intel/broadwell/cpu.c
@@ -290,22 +290,6 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
-static void configure_thermal_target(void)
-{
- config_t *conf = config_of_soc();
- msr_t msr;
-
-
- /* Set TCC activation offset if supported */
- msr = rdmsr(MSR_PLATFORM_INFO);
- if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
- msr = rdmsr(MSR_TEMPERATURE_TARGET);
- msr.lo &= ~(0xf << 24); /* Bits 27:24 */
- msr.lo |= (conf->tcc_offset & 0xf) << 24;
- wrmsr(MSR_TEMPERATURE_TARGET, msr);
- }
-}
-
static void configure_misc(void)
{
msr_t msr;
@@ -430,7 +414,7 @@ static void cpu_core_init(struct device *cpu)
configure_misc();
/* Thermal throttle activation offset */
- configure_thermal_target();
+ configure_tcc_thermal_target();
/* Enable Direct Cache Access */
configure_dca_cap();