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-rw-r--r--src/soc/intel/braswell/Kconfig1
-rw-r--r--src/soc/intel/braswell/acpi/device_nvs.asl124
-rw-r--r--src/soc/intel/braswell/acpi/globalnvs.asl5
-rw-r--r--src/soc/intel/braswell/acpi/platform.asl3
-rw-r--r--src/soc/intel/braswell/include/soc/device_nvs.h4
-rw-r--r--src/soc/intel/braswell/include/soc/nvs.h10
-rw-r--r--src/soc/intel/braswell/lpe.c17
-rw-r--r--src/soc/intel/braswell/lpss.c15
-rw-r--r--src/soc/intel/braswell/scc.c15
9 files changed, 87 insertions, 107 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index dcc30ee567..001cab7960 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -8,6 +8,7 @@ if SOC_INTEL_BRASWELL
config CPU_SPECIFIC_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+ select ACPI_HAS_DEVICE_NVS
select ARCH_ALL_STAGES_X86_32
select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
select BOOT_DEVICE_SUPPORTS_WRITES
diff --git a/src/soc/intel/braswell/acpi/device_nvs.asl b/src/soc/intel/braswell/acpi/device_nvs.asl
index 3722856331..aa0e9533f8 100644
--- a/src/soc/intel/braswell/acpi/device_nvs.asl
+++ b/src/soc/intel/braswell/acpi/device_nvs.asl
@@ -1,68 +1,74 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* Device Enabled in ACPI Mode */
+External (NVSD)
-S0EN, 8, /* SDMA Enable */
-S1EN, 8, /* I2C1 Enable */
-S2EN, 8, /* I2C2 Enable */
-S3EN, 8, /* I2C3 Enable */
-S4EN, 8, /* I2C4 Enable */
-S5EN, 8, /* I2C5 Enable */
-S6EN, 8, /* I2C6 Enable */
-S7EN, 8, /* I2C7 Enable */
-S8EN, 8, /* SDMA2 Enable */
-S9EN, 8, /* SPI Enable */
-SAEN, 8, /* PWM1 Enable */
-SBEN, 8, /* PWM2 Enable */
-SCEN, 8, /* UART2 Enable */
-SDEN, 8, /* UART2 Enable */
-C0EN, 8, /* MMC Enable */
-C1EN, 8, /* SDIO Enable */
-C2EN, 8, /* SD Card Enable */
-LPEN, 8, /* LPE Enable */
+OperationRegion (DNVS, SystemMemory, NVSD, 0x1000)
+Field (DNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Device Enabled in ACPI Mode */
-/* BAR 0 */
+ S0EN, 8, /* SDMA Enable */
+ S1EN, 8, /* I2C1 Enable */
+ S2EN, 8, /* I2C2 Enable */
+ S3EN, 8, /* I2C3 Enable */
+ S4EN, 8, /* I2C4 Enable */
+ S5EN, 8, /* I2C5 Enable */
+ S6EN, 8, /* I2C6 Enable */
+ S7EN, 8, /* I2C7 Enable */
+ S8EN, 8, /* SDMA2 Enable */
+ S9EN, 8, /* SPI Enable */
+ SAEN, 8, /* PWM1 Enable */
+ SBEN, 8, /* PWM2 Enable */
+ SCEN, 8, /* UART2 Enable */
+ SDEN, 8, /* UART2 Enable */
+ C0EN, 8, /* MMC Enable */
+ C1EN, 8, /* SDIO Enable */
+ C2EN, 8, /* SD Card Enable */
+ LPEN, 8, /* LPE Enable */
-S0B0, 32, /* SDMA BAR0 */
-S1B0, 32, /* I2C1 BAR0 */
-S2B0, 32, /* I2C2 BAR0 */
-S3B0, 32, /* I2C3 BAR0 */
-S4B0, 32, /* I2C4 BAR0 */
-S5B0, 32, /* I2C5 BAR0 */
-S6B0, 32, /* I2C6 BAR0 */
-S7B0, 32, /* I2C7 BAR0 */
-S8B0, 32, /* SDMA2 BAR0 */
-S9B0, 32, /* SPI BAR0 */
-SAB0, 32, /* PWM1 BAR0 */
-SBB0, 32, /* PWM2 BAR0 */
-SCB0, 32, /* UART1 BAR0 */
-SDB0, 32, /* UART2 BAR0 */
-C0B0, 32, /* MMC BAR0 */
-C1B0, 32, /* SDIO BAR0 */
-C2B0, 32, /* SD Card BAR0 */
-LPB0, 32, /* LPE BAR0 */
+ /* BAR 0 */
-/* BAR 1 */
+ S0B0, 32, /* SDMA BAR0 */
+ S1B0, 32, /* I2C1 BAR0 */
+ S2B0, 32, /* I2C2 BAR0 */
+ S3B0, 32, /* I2C3 BAR0 */
+ S4B0, 32, /* I2C4 BAR0 */
+ S5B0, 32, /* I2C5 BAR0 */
+ S6B0, 32, /* I2C6 BAR0 */
+ S7B0, 32, /* I2C7 BAR0 */
+ S8B0, 32, /* SDMA2 BAR0 */
+ S9B0, 32, /* SPI BAR0 */
+ SAB0, 32, /* PWM1 BAR0 */
+ SBB0, 32, /* PWM2 BAR0 */
+ SCB0, 32, /* UART1 BAR0 */
+ SDB0, 32, /* UART2 BAR0 */
+ C0B0, 32, /* MMC BAR0 */
+ C1B0, 32, /* SDIO BAR0 */
+ C2B0, 32, /* SD Card BAR0 */
+ LPB0, 32, /* LPE BAR0 */
-S0B1, 32, /* SDMA BAR1 */
-S1B1, 32, /* I2C1 BAR1 */
-S2B1, 32, /* I2C2 BAR1 */
-S3B1, 32, /* I2C3 BAR1 */
-S4B1, 32, /* I2C4 BAR1 */
-S5B1, 32, /* I2C5 BAR1 */
-S6B1, 32, /* I2C6 BAR1 */
-S7B1, 32, /* I2C7 BAR1 */
-S8B1, 32, /* SDMA2 BAR1 */
-S9B1, 32, /* SPI BAR1 */
-SAB1, 32, /* PWM1 BAR1 */
-SBB1, 32, /* PWM2 BAR1 */
-SCB1, 32, /* UART1 BAR1 */
-SDB1, 32, /* UART2 BAR1 */
-C0B1, 32, /* MMC BAR1 */
-C1B1, 32, /* SDIO BAR1 */
-C2B1, 32, /* SD Card BAR1 */
-LPB1, 32, /* LPE BAR1 */
+ /* BAR 1 */
-/* Extra */
+ S0B1, 32, /* SDMA BAR1 */
+ S1B1, 32, /* I2C1 BAR1 */
+ S2B1, 32, /* I2C2 BAR1 */
+ S3B1, 32, /* I2C3 BAR1 */
+ S4B1, 32, /* I2C4 BAR1 */
+ S5B1, 32, /* I2C5 BAR1 */
+ S6B1, 32, /* I2C6 BAR1 */
+ S7B1, 32, /* I2C7 BAR1 */
+ S8B1, 32, /* SDMA2 BAR1 */
+ S9B1, 32, /* SPI BAR1 */
+ SAB1, 32, /* PWM1 BAR1 */
+ SBB1, 32, /* PWM2 BAR1 */
+ SCB1, 32, /* UART1 BAR1 */
+ SDB1, 32, /* UART2 BAR1 */
+ C0B1, 32, /* MMC BAR1 */
+ C1B1, 32, /* SDIO BAR1 */
+ C2B1, 32, /* SD Card BAR1 */
+ LPB1, 32, /* LPE BAR1 */
-LPFW, 32, /* LPE BAR2 Firmware */
+ /* Extra */
+
+ LPFW, 32, /* LPE BAR2 Firmware */
+}
diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl
index 564eb43788..6aa595713b 100644
--- a/src/soc/intel/braswell/acpi/globalnvs.asl
+++ b/src/soc/intel/braswell/acpi/globalnvs.asl
@@ -13,7 +13,7 @@ Name(\PICM, 0) /* IOAPIC/8259 */
External (NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x1000)
Field (GNVS, ByteAcc, NoLock, Preserve)
{
/* Miscellaneous */
@@ -58,9 +58,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* ChromeOS specific */
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
-
- Offset (0x1000),
- #include <soc/intel/braswell/acpi/device_nvs.asl>
}
/* Set flag to enable USB charging in S3 */
diff --git a/src/soc/intel/braswell/acpi/platform.asl b/src/soc/intel/braswell/acpi/platform.asl
index 7fd3984e40..6a01c28e9c 100644
--- a/src/soc/intel/braswell/acpi/platform.asl
+++ b/src/soc/intel/braswell/acpi/platform.asl
@@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <soc/intel/braswell/acpi/device_nvs.asl>
+
/* Enable ACPI _SWS methods */
#include <soc/intel/common/acpi/acpi_wake_source.asl>
#include <southbridge/intel/common/acpi/platform.asl>
-
/*
* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 73af09ad41..bf8974d840 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -24,7 +24,7 @@
#define SCC_NVS_SDIO 1
#define SCC_NVS_SD 2
-typedef struct {
+struct __packed device_nvs {
/* Device Enabled in ACPI Mode */
u8 lpss_en[14];
u8 scc_en[3];
@@ -42,6 +42,6 @@ typedef struct {
/* Extra */
u32 lpe_fw; /* LPE Firmware */
-} __packed device_nvs_t;
+};
#endif /* _SOC_DEVICE_NVS_H_ */
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 41bb5a1a54..7d27c3f822 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -4,7 +4,6 @@
#define _SOC_NVS_H_
#include <stdint.h>
-#include <soc/device_nvs.h>
struct __packed global_nvs {
/* Miscellaneous */
@@ -45,15 +44,6 @@ struct __packed global_nvs {
u32 obsolete_cmem; /* 0x30 - CBMEM TOC */
u32 tolm; /* 0x34 - Top of Low Memory */
u32 cbmc; /* 0x38 - coreboot memconsole */
- u8 rsvd3[120]; /* 0x3c - 0xb3 - unused */
-
- u8 unused[76];
-
- /* ChromeOS specific (0x100-0xfff) */
- u8 chromeos_reserve[0xf00];
-
- /* LPSS (0x1000) */
- device_nvs_t dev;
};
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 14be808136..59cabee707 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -12,7 +12,7 @@
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/lpc.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
@@ -53,20 +53,15 @@ static void lpe_enable_acpi_mode(struct device *dev)
REG_SCRIPT_END
};
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0, BAR1, and firmware base to ACPI NVS */
- assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
- assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2);
- assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
+ assign_device_nvs(dev, &dev_nvs->lpe_bar0, PCI_BASE_ADDRESS_0);
+ assign_device_nvs(dev, &dev_nvs->lpe_bar1, PCI_BASE_ADDRESS_2);
+ assign_device_nvs(dev, &dev_nvs->lpe_fw, FIRMWARE_PCI_REG_BASE);
/* Device is enabled in ACPI mode */
- gnvs->dev.lpe_en = 1;
+ dev_nvs->lpe_en = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 961d405156..93ee3da273 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -9,7 +9,7 @@
#include <reg_script.h>
#include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -28,24 +28,19 @@ static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index
REG_SCRIPT_END
};
struct resource *bar;
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
- gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base;
+ dev_nvs->lpss_bar0[nvs_index] = (u32)bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_1);
if (bar)
- gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base;
+ dev_nvs->lpss_bar1[nvs_index] = (u32)bar->base;
/* Device is enabled in ACPI mode */
- gnvs->dev.lpss_en[nvs_index] = 1;
+ dev_nvs->lpss_en[nvs_index] = 1;
/* Put device in ACPI mode */
reg_script_run_on_dev(dev, ops);
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 45ce8de982..c6d4f5201e 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -5,27 +5,22 @@
#include <device/device.h>
#include <device/pci.h>
#include <soc/iosf.h>
-#include <soc/nvs.h>
+#include <soc/device_nvs.h>
#include <soc/ramstage.h>
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct resource *bar;
- struct global_nvs *gnvs;
-
- /* Find ACPI NVS to update BARs */
- gnvs = acpi_get_gnvs();
- if (!gnvs)
- return;
+ struct device_nvs *dev_nvs = acpi_get_device_nvs();
/* Save BAR0 and BAR1 to ACPI NVS */
bar = find_resource(dev, PCI_BASE_ADDRESS_0);
if (bar)
- gnvs->dev.scc_bar0[nvs_index] = bar->base;
+ dev_nvs->scc_bar0[nvs_index] = bar->base;
bar = find_resource(dev, PCI_BASE_ADDRESS_2);
if (bar)
- gnvs->dev.scc_bar1[nvs_index] = bar->base;
+ dev_nvs->scc_bar1[nvs_index] = bar->base;
/* Device is enabled in ACPI mode */
- gnvs->dev.scc_en[nvs_index] = 1;
+ dev_nvs->scc_en[nvs_index] = 1;
}