diff options
Diffstat (limited to 'src/soc/intel/braswell/Kconfig')
| -rw-r--r-- | src/soc/intel/braswell/Kconfig | 169 |
1 files changed, 77 insertions, 92 deletions
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index d4200c77c6..dac38cec14 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -1,31 +1,45 @@ config SOC_INTEL_BRASWELL bool help - Bay Trail M/D part support. + Braswell M/D part support. if SOC_INTEL_BRASWELL config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select CACHE_ROM + select CAR_MIGRATION select COLLECT_TIMESTAMPS + select CPU_MICROCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select SUPPORT_CPU_UCODE_IN_CBFS + select DYNAMIC_CBMEM + select ENABLE_MRC_CACHE + select HAS_PRECBMEM_TIMESTAMP_REGION + select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES - select RELOCATABLE_RAMSTAGE select PARALLEL_MP select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK + select PLATFORM_USES_FSP1_1 select REG_SCRIPT + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_FSP_RAM_INIT + select SOC_INTEL_COMMON_FSP_ROMSTAGE + select SOC_INTEL_COMMON_RESET + select SOC_INTEL_COMMON_STACK + select SOC_INTEL_COMMON_STAGE_CACHE + select SMM_MODULES select SMM_TSEG select SMP select SPI_FLASH @@ -35,14 +49,14 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select SOC_INTEL_COMMON + select USE_GENERIC_FSP_CAR_INC config BOOTBLOCK_CPU_INIT string - default "soc/intel/baytrail/bootblock/bootblock.c" + default "soc/intel/braswell/bootblock/bootblock.c" config MMCONF_BASE_ADDRESS - hex + hex "PCIe CFG Base Address" default 0xe0000000 config MAX_CPUS @@ -61,39 +75,8 @@ config SMM_RESERVED_SIZE hex default 0x100000 -config HAVE_MRC - bool "Add a Memory Reference Code binary" - default y - help - Select this option to add a blob containing - memory reference code. - Note: Without this binary coreboot will not work - -if HAVE_MRC - -config MRC_FILE - string "Intel memory refeference code path and filename" - default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin" - help - The path and filename of the file to use as System Agent - binary. Note that this points to the sandybridge binary file - which is will not work, but it serves its purpose to do builds. - -config MRC_BIN_ADDRESS - hex - default 0xfffa0000 - -config MRC_RMT - bool "Enable MRC RMT training + debug prints" - default n - -endif # HAVE_MRC - # Cache As RAM region layout: # -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE -# | MRC usage | -# | | # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE # | Stack |\ # | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE @@ -104,48 +87,63 @@ endif # HAVE_MRC # | CAR Globals | # +-------------+ DCACHE_RAM_BASE # -# Note that the MRC binary is linked to assume the region marked as "MRC usage" -# starts at DCACHE_RAM_BASE + DCACHE_RAM_SIZE. If those values change then -# a new MRC binary needs to be produced with the updated start and size -# information. config DCACHE_RAM_BASE - hex - default 0xfe000000 + hex "Temporary RAM Base Address" + default 0xfef00000 config DCACHE_RAM_SIZE - hex - default 0x8000 + hex "Temporary RAM Size" + default 0x4000 help The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. -config DCACHE_RAM_MRC_VAR_SIZE - hex - default 0x8000 - help - The amount of cache-as-ram region required by the reference code. - config DCACHE_RAM_ROMSTAGE_STACK_SIZE hex default 0x800 help The amount of anticipated stack usage from the data cache - during pre-RAM ROM stage execution. + during pre-ram rom stage execution. config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n depends on RELOCATABLE_RAMSTAGE help - The baytrail romstage code caches the loaded ramstage program + The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs. +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0x100000 + help + The firmware image has to store a lot more than just coreboot, + including: + - a firmware descriptor + - Intel Management Engine firmware + - MRC cache information + This option allows to limit the size of the CBFS portion in the + firmware image. + +config LOCK_MANAGEMENT_ENGINE + bool "Lock Management Engine section" + default n + help + The Intel Management Engine supports preventing write accesses + from the host to the Management Engine section in the firmware + descriptor. If the ME section is locked, it can only be overwritten + with an external SPI flash programmer. You will want this if you + want to increase security of your ROM image once you are sure + that the ME firmware is no longer going to change. + + If unsure, say N. + config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n @@ -154,22 +152,6 @@ config ENABLE_BUILTIN_COM1 configure the pads and enable it. This serial port can be used for the debug console. -config HAVE_ME_BIN - bool "Add Intel Management Engine firmware" - default y - help - The Intel processor in the selected system requires a special firmware - for an integrated controller called Management Engine (ME). The ME - firmware might be provided in coreboot's 3rdparty repository. If - not and if you don't have the firmware elsewhere, you can still - build coreboot without it. In this case however, you'll have to make - sure that you don't overwrite your ME firmware on your flash ROM. - -config ME_BIN_PATH - string "Path to management engine firmware" - depends on HAVE_ME_BIN - default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" - config HAVE_IFD_BIN bool default y @@ -191,6 +173,26 @@ config BUILD_WITH_FAKE_IFD [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html +config HAVE_ME_BIN + bool "Add Intel Management Engine firmware" + default y + help + The Intel processor in the selected system requires a special firmware + for an integrated controller called Management Engine (ME). The ME + firmware might be provided in coreboot's 3rdparty/blobs repository. If + not and if you don't have the firmware elsewhere, you can still + build coreboot without it. In this case however, you'll have to make + sure that you don't overwrite your ME firmware on your flash ROM. + +config IED_REGION_SIZE + hex + default 0x400000 + +config IFD_BIN_PATH + string "Path to intel firmware descriptor" + depends on !BUILD_WITH_FAKE_IFD + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" + config IFD_BIOS_SECTION depends on BUILD_WITH_FAKE_IFD string @@ -206,26 +208,9 @@ config IFD_PLATFORM_SECTION string default "" -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - depends on !BUILD_WITH_FAKE_IFD - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" - -config HAVE_REFCODE_BLOB - depends on ARCH_X86 - bool "An external reference code blob should be put into cbfs." - default n - help - The reference code blob will be placed into cbfs. - -if HAVE_REFCODE_BLOB - -config REFCODE_BLOB_FILE - string "Path and filename to reference code blob." - default "refcode.elf" - help - The path and filename to the file to be added to cbfs. - -endif # HAVE_REFCODE_BLOB +config ME_BIN_PATH + string "Path to management engine firmware" + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" endif |