2 files changed, 15 insertions, 15 deletions

diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 0784f69cf8..d45b9eab26 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -14,6 +14,7 @@
  */
 
 #include <stddef.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <bootmode.h>
 #include <cbfs.h>
@@ -127,7 +128,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	} else if (!mrc_cache_get_current(&cache)) {
 		mp->saved_data_size = cache->size;
 		mp->saved_data = &cache->data[0];
-	} else if (prev_sleep_state == 3) {
+	} else if (prev_sleep_state == ACPI_S3) {
 		/* If waking from S3 and no cache then. */
 		printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n");
 		post_code(POST_RESUME_FAILURE);
@@ -135,7 +136,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	} else {
 		printk(BIOS_DEBUG, "No MRC cache found.\n");
 #if CONFIG_EC_GOOGLE_CHROMEEC
-		if (prev_sleep_state == 0) {
+		if (prev_sleep_state == ACPI_S0) {
 			/* Ensure EC is running RO firmware. */
 			google_chromeec_check_ec_image(EC_IMAGE_RO);
 		}
@@ -162,7 +163,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 
 	print_dram_info();
 
-	if (prev_sleep_state != 3) {
+	if (prev_sleep_state != ACPI_S3) {
 		cbmem_initialize_empty();
 	} else if (cbmem_initialize()) {
 	#if CONFIG_HAVE_ACPI_RESUME
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index d7e8b17648..96ae86dd63 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -184,17 +184,16 @@ static struct chipset_power_state *fill_power_state(void)
 static int chipset_prev_sleep_state(struct chipset_power_state *ps)
 {
 	/* Default to S0. */
-	int prev_sleep_state = 0;
+	int prev_sleep_state = ACPI_S0;
 
 	if (ps->pm1_sts & WAK_STS) {
-		switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
-	#if CONFIG_HAVE_ACPI_RESUME
-		case SLP_TYP_S3:
-			prev_sleep_state = 3;
+		switch (acpi_sleep_from_pm1(ps->pm1_cnt)) {
+		case ACPI_S3:
+			if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
+				prev_sleep_state = ACPI_S3;
 			break;
-	#endif
-		case SLP_TYP_S5:
-			prev_sleep_state = 5;
+		case ACPI_S5:
+			prev_sleep_state = ACPI_S5;
 			break;
 		}
 		/* Clear SLP_TYP. */
@@ -202,7 +201,7 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
 	}
 
 	if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) {
-		prev_sleep_state = 5;
+		prev_sleep_state = ACPI_S5;
 	}
 
 	return prev_sleep_state;
@@ -223,7 +222,7 @@ void romstage_common(struct romstage_params *params)
 	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 
 #if CONFIG_ELOG_BOOT_COUNT
-	if (prev_sleep_state != 3)
+	if (prev_sleep_state != ACPI_S3)
 		boot_count_increment();
 #endif
 
@@ -235,12 +234,12 @@ void romstage_common(struct romstage_params *params)
 
 	handoff = romstage_handoff_find_or_add();
 	if (handoff != NULL)
-		handoff->s3_resume = (prev_sleep_state == 3);
+		handoff->s3_resume = (prev_sleep_state == ACPI_S3);
 	else
 		printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
 
 	if (IS_ENABLED(CONFIG_LPC_TPM)) {
-		init_tpm(prev_sleep_state == 3);
+		init_tpm(prev_sleep_state == ACPI_S3);
 	}
 }