diff options
Diffstat (limited to 'src/soc/intel/baytrail/romstage/pmc.c')
| -rw-r--r-- | src/soc/intel/baytrail/romstage/pmc.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c new file mode 100644 index 0000000000..e689ccd527 --- /dev/null +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <arch/io.h> +#include <baytrail/iomap.h> +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> +#include <baytrail/romstage.h> + +void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} |