1 files changed, 33 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/car.c b/src/soc/intel/apollolake/car.c
new file mode 100644
index 0000000000..7646865ca2
--- /dev/null
+++ b/src/soc/intel/apollolake/car.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/cpu.h>
+#include <program_loading.h>
+#include <soc/cpu.h>
+
+/*
+ * This file supports the necessary hoops one needs to jump through since
+ * early FSP component and early stages are running from cache-as-ram.
+ */
+
+static void flush_l1d_to_l2(void)
+{
+	msr_t msr = rdmsr(MSR_POWER_MISC);
+	msr.lo |= (1 << 8);
+	wrmsr(MSR_POWER_MISC, msr);
+}
+
+void platform_prog_run(struct prog *prog)
+{
+	/* Flush L1D cache to L2 */
+	flush_l1d_to_l2();
+}