diff options
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 8e59c9ad5c..f23b9d2566 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/pcie_rp.h> #include <soc/gpe.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -136,12 +137,7 @@ struct soc_intel_alderlake_config { uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; |