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-rw-r--r--src/soc/intel/alderlake/include/soc/romstage.h11
-rw-r--r--src/soc/intel/alderlake/romstage/romstage.c7
2 files changed, 17 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h
index 679d538b2d..574c9b7ae1 100644
--- a/src/soc/intel/alderlake/include/soc/romstage.h
+++ b/src/soc/intel/alderlake/include/soc/romstage.h
@@ -20,4 +20,15 @@ enum board_type {
BOARD_TYPE_SERVER = 8
};
+/*
+ * Default implementation indicates that the mainboard does not expect another reset.
+ * Mainboards can override the default implementation to indicate whether they expect
+ * another reset eg. FW Sync for another component on the mainboard. Some silicon init
+ * code eg. disabling UFS, can use this hint to suppress any redundant resets that they
+ * trigger. If the mainboard does not expect another reset, then the silicon init code
+ * can trigger their required reset.
+ *
+ * Return: true when the mainboard expects another reset, false otherwise.
+ */
+bool mainboard_expects_another_reset(void);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ff600db7b0..2f50cd29dd 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -32,6 +32,11 @@
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
+bool __weak mainboard_expects_another_reset(void)
+{
+ return false;
+}
+
static void disable_ufs(void)
{
/* disable USF0 */
@@ -185,7 +190,7 @@ void mainboard_romstage_entry(void)
(CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
printk(BIOS_INFO, "Disabling UFS controllers\n");
disable_ufs();
- if (ps->prev_sleep_state == ACPI_S5) {
+ if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
system_reset();
}